Scientific Publications and White Papers by GTS Staff
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Performance Degradation Mechanisms in p-Type Nanosheet FETs: Role of Source/Drain Doping, Stress, and Inner Spacer Interface Traps
The performance of p-type nanosheet FETs (NSFETs) with embedded SiGe (eSiGe) source/drain (S/D) is investigated by solving the subband Boltzmann transport equation (SBTE), highlighting three detrimental effects of aggressive scaling: 1) insufficient extension doping; 2) stress relaxation during the merging of epitaxial growth fronts; and 3) interface trap density (Dit) at the Si/SiN interfaces. An optimal doping window of the first epitaxial layer (L1) between 5 × 10^19 and 2 × 10^20 cm−3 is identified to maintain gate-controlled operation. Below this range, the device enters the injection-limited transport regime, where stress relaxation and Dit-induced injection barriers are significantly amplified, leading to pronounced performance degradation. These results highlight the critical role of L1 doping optimization for effective stress engineering and Dit mitigation, and underscore the necessity of non-equilibrium transport modeling for highly-scaled NSFETs.
Terman Method to Study Threshold Voltage Hysteresis of Si/SiGe Heterostructures at Cryogenic Temperatures
Semiconductor device reliability at cryogenic temperatures has emerged as an important research area driven by quantum computing applications. Si/SiGe heterostructures have established themselves as a leading platform for quantum devices, yet charge trapping at interfaces remains a key reliability concern. This work presents a phenomenological approach to characterize interface trapping in Si/SiGe heterostacks using fixed charge approximations. We demonstrate that threshold voltage hysteresis observed in capacitance-voltage measurements from 4.2 K to 80 K can be accurately modeled by assigning fixed charges at each channel interface. By combining this methodology with the Terman method, we extract the trap energy distribution, revealing a peak located approximately 0.1 eV below the conduction band with a maximum density of $5 imes 10^12 extcm^-2 exteV^-1$. The extracted distributions show strong agreement with interface trap density of states reported in literature, supporting the hypothesis that fast-responding interface traps are the primary mechanism driving the observed hysteresis.
On-Current Degradation in Ultra-Scaled Nanosheet FETs with S/D Underlap Doping
Aggressive gate pitch scaling makes it increasingly challenging to control the doping gradient at the source/drain (S/D) extensions. To address this, S/D underlap doping has been proposed as a solution. However, anomalous ID,lin saturation has been experimentally observed in such devices, raising questions about its physical origin. In this work, we investigate the transport physics in ultra-scaled nanosheet FETs by solving the Subband Boltzmann Transport Equation. The simulation results reveal that secondary barriers formed in underdoped S/D extensions enhance quasi-ballistic transport even in the linear regime, providing a consistent explanation for the observed ID,lin saturation in underlap devices. These insights offer guidance for optimizing S/D underlap doping profiles, highlighting the need to avoid excessive Gate-S/D overlap capacitance while preventing on-current degradation.
Revealing the Partially Coherent Nature of Transport in IGZO
Thin-film transistors based on amorphous oxide semiconductors (AOS) are promising candidates for enabling further DRAM scaling and 3D integration, which are critical for advanced computing. Despite extensive research, the charge transport mechanism in these disordered semiconductors remains poorly understood. In this work, we investigate charge transport in the archetypical AOS material, indium gallium zinc oxide (IGZO), across a range of compositions and temperatures using thin-film transistors and Hall bar structures. Our results show that the electrons involved in transport exhibit partially spatial coherence and non-degenerate conduction. Under these conditions, transport is dominated by electron transfer across insulating gaps between locally coherent regions, rather than by degenerate percolative transport above a mobility edge, or by localized-state hopping, both of which are widely assumed in the literature. While fluctuation-induced tunnelling has previously been invoked to describe low-temperature transport in oxide transistors, we show that such behavior originates from partially coherent electronic states and develop a field-effect-aware fluctuation-induced tunnelling (FEAFIT) framework that explicitly accounts for gate modulation of the tunneling landscape. The FEAFIT model accurately predicts experimental data across all compositions, temperatures, and gate voltages, enabling extraction of fundamental transport parameters. These tunnelling parameters are then correlated with electron coherence dimensions and the degree of energetic disorder obtained from first-principles calculations. Our findings advance the fundamental understanding of charge transport in AOS-based transistors and provide a foundation for further performance improvements
TCAD Analysis on the Geometry Effects in Three-Independent-Gates Reconfigurable FETs
The n-type and p-type operations of 22 nm Fully Depleted Silicon on Insulator (FDSOI) Three-Independent-Gates Reconfigurable Field Effect Transistors (TIG-RFETs) are simulated, incorporating Schottky contacts to the drift-diffusion model. Key-features are selected and adjusted to fit experimental results, like: Schottky barrier height (SBH), direct tunnelling and presence of traps. The inclusion and correct adjustment of these parameters reveals the importance of strong electrostatic control over the energetic barrier at the metal-semiconductor junctions. We extend this analysis with a study of the theoretical impact of the metal-semiconductor interface position under the sourcedrain gates coupled with the length of the ungated regions.
An Effective-Medium TCAD Model of Amorphous In-Ga-Zn-O (a-IGZO) Suitable for Large-Area Devices
IGZO is a disordered material whose transport is typified by percolative flow through a rolling landscape of a spatially-varying conduction-band-edge. Our previous Microscopic TCAD model of a-IGZO replicated percolative flow via directly simulating this spatial variation. However, this is difficult for large-area devices as it requires fine spatial resolution. Here we introduce a new Effective-Medium TCAD model that is shown to be accurate (relative to both the Microscopic model and experiment) in the coarse-gridding and largedevice regime.
Is There Anything Left to Do in TCAD?
Over the past decade, the development of commercial technology computer-aided design (TCAD) software has followed an evolutionary rather than revolutionary path. Alongside established continuum and particle-based approaches in both process and device simulation, advanced carrier transport models - such as deterministic bulk and subband Boltzmann transport equation (BTE) solvers and non-equilibrium Green's functions (NEGF) - have been incorporated into the TCAD toolkit for single-device simulation. At the system level, the field of designtechnology co-optimization (DTCO) has expanded to encompass variability, reliability, and the extension of TCAD methodologies from devices to circuits. However, most of these innovations were introduced over a decade ago, prompting the question: What remains to be developed in TCAD? We address this question by analyzing current limitations and potential future directions in TCAD development across three key dimensions: (1) fidelity, (2) integration, and (3) efficiency - each with particular relevance in commercial and industrial contexts. We examine ongoing challenges in classical TCAD, advanced transport modeling, and DTCO flows, and point to potential directions for future developments. Among these, we include various methodologies related to machine learning and hardware accelerators, particularly within the efficiency dimension.
Overview of emerging semiconductor device model methodologies: From device physics to machine learning engines
Advancements in the semiconductor industry introduce novel channel materials, device structures, and integration methods, leading to intricate physics challenges when characterizing devices at circuit level. Nevertheless, accurate models for emerging devices are crucial for physics-driven TCAD-to-SPICE flows to enable the increasingly vital design technology co-optimization (DTCO). Particularly for ultra-scaled devices where quantum effects become significant, this led to the introduction of empirical model parameters and a disconnection to manufacturing processes. To catch up with these developments, an alternative to the traditional white-box modeling methods has attracted much attention: machine learning-assisted compact modeling (MLCM). These black-box methods target towards general-purpose modeling of complex mathematics and physics through training of neural networks on experimental and simulated data, generating an accurate closed-form mapping between output characteristics and input parameters for fabrication process and device operation. To address this new trend, this work provides a comprehensive overview of emerging device model methodologies, spanning from device physics to machine learning engines. By analyzing, structuring, and extending distributed efforts on this topic, it is shown how MLCM can overcome limitations of traditional compact modeling and contribute to effective DTCO to further advance semiconductor technologies.
An Experimentally Validated TCAD Variability Study of The Relative Performance of In-Ga-Zn-O And Poly-Si-Channel Ferroelectric VNANDs
Memories based on a VNAND structure - whether ferroelectric or charge-trap-based - often suffer from performance issues related to the generally poor quality of their polycrystalline silicon (poly Si) channels. In-Ga-Zn-O (IGZO) has been suggested as an alternative material due to its proven history in thin-film applications. In this work TCAD models are developed that model the variability of polycrystalline silicon, amorphous IGZO and polycrystalline ferroelectric HfZrO2 (HZO) thin layers. All models are validated against experimental results and a complete parameter set for the variability models is given. The models are then used to assess the impact of selecting an IGZO-based device over a poly-Si device on the performance of a ferroelectric bit cell.
Exploring GAA-Nanosheet, Forksheet and GAA-Forksheet Architectures: A TCAD-DTCO Study at 90~nm and 120~nm Cell Height
This study presents a Technology Computer Aided Design (TCAD) and comprehensive Design-Technology Co-Optimization (DTCO) approach to evaluate and enhance power and performance in Gate-All-Around Nanosheet (GAA-Nsh) and Forksheet (Fsh) architectures. The analysis focuses on the impact of active widths, sheet count, wall properties, and power delivery methods on the effective resistance (Reff) and capacitance (Ceff) of these devices. The research employs simulations of five-stage INVD1 ring oscillators (RO) at various metal pitches (Mx) to extract frequency and power data. Notably, a novel Gate-All-Around Forksheet (GAA-Fsh) structure is introduced, offering enhanced gate control while retaining the advantages of Fsh. The study also explores asymmetric N/PFETs within the Fsh technology, and innovative contacting approaches such as Buried Power Rail (BPR) and Backside Power Rail (BS-PR) with Backside Contact (BSC) to reduce access resistance. Results indicate that GAA-Fsh outperforms traditional GAA-Nsh and Fsh due to reduced Reff and Ceff, although it is process feasible only at larger Mx. At smaller Mx, GAA-Nsh demonstrates higher performance than Fsh at a given sheet width (Wsh), but Fsh, with the advantage of additional Wsh, can match GAA-Nsh performance at larger Wsh. Furthermore, the BPR and BS-PR contacting schemes are found to provide similar performance. This research provides valuable insights into future semiconductor device designs, emphasizing higher performance and efficient scaling.
Exploring GAA-Nanosheet, Forksheet and GAA–Forksheet Architectures: A TCAD-DTCO Study at 90 nm and 120-nm Cell Height
This study presents a Technology Computer Aided Design (TCAD) and comprehensive Design-Technology Co-Optimization (DTCO) approach to evaluate and enhance power and performance in Gate-All-Around Nanosheet (GAA-Nsh) and Forksheet (Fsh) architectures. The analysis focuses on the impact of active widths, sheet count, wall properties, and power delivery methods on the effective resistance (Reff) and capacitance (Ceff) of these devices. The research employs simulations of five-stage INVD1 ring oscillators (RO) at various metal pitches (Mx) to extract frequency and power data. Notably, a novel Gate-All-Around Forksheet (GAA-Fsh) structure is introduced, offering enhanced gate control while retaining the advantages of Fsh. The study also explores asymmetric N/PFETs within the Fsh technology, and innovative contacting approaches such as Buried Power Rail (BPR) and Backside Power Rail (BS-PR) with Backside Contact (BSC) to reduce access resistance. Results indicate that GAA-Fsh outperforms traditional GAA-Nsh and Fsh due to reduced Reff and Ceff, although it is process feasible only at larger Mx. At smaller Mx, GAA-Nsh demonstrates higher performance than Fsh at a given sheet width (Wsh), but Fsh, with the advantage of additional Wsh, can match GAA-Nsh performance at larger Wsh. Furthermore, the BPR and BS-PR contacting schemes are found to provide similar performance. This research provides valuable insights into future semiconductor device designs, emphasizing higher performance and efficient scaling.
TCAD for Circuits and Systems: Process Emulation, Parasitics Extraction, Self-Heating
We present TCAD-based methodologies that go beyond process and device simulations of single transistors. We show that TCAD solvers can be used as effective tools to resolve the intricacies of current and future technology nodes that are otherwise difficult to access using EDA-level methods alone.
3D VNWFET-Based Standard Cell Library Design Flow: from Circuit and Physical Design to Logic Synthesis
The vertical nanowire field effect transistor (VN-WFET) is an emerging technology that promises to improve the sustainability of future transistor scaling beyond the limitations of conventional lateral devices. With its 3D gate-all-around (GAA) architecture, such a technology enables designs with improved energy-efficiency as well as reduced footprint and thus interconnect capacitance. In this work, and based on the compact model of a real VNWFET device, we present the design flow for the generation of a standard cell library starting from the circuit and physical design of logic cells to logic synthesis based on the VNWFET technology. The results on the synthesized benchmark cells, as compared against 45nm and 65nm CMOS libraries, demonstrate a significant decrease in the average dynamic power consumption and delay values up to 71X and 34X respectively, with an average area gain of up to 5X. However, an increase in leakage power consumption (up to 2X on average) was also observed.
On the Potential of Ambipolar Schottky-Based Ferroelectric Transistor Designs for Enhanced Memory Windows in Scaled Devices
Ferroelectric memory devices have seen intense interest over the last decade. However, in heavily scaled devices such as silicon-on-insulator (SOI), FinFETs, and nanowire-based FETs the observed ferroelectric memory window (MW) is heavily degraded owing to the fact that additional majority carriers cannot be sourced as there is no “bulk.” Thus, the device never enters accumulation and polarization switching is suppressed due to the semiconductor channel remaining depleted. Here, we promote an ambipolar Schottky-based ferroelectric transistor (AS-FeFET) as an alternative design. We demonstrate that such devices—owing to their ambipolar nature and thus the ability to source both types of carriers—exhibit MWs that are consistently ∼ 40%–60% larger than conventional devices for the same programming conditions. Although these devices do suffer from a reduced ON-current, this tradeoff remains very attractive for many applications.
Hierarchical Transport Modeling for Path-Finding DTCO
We present a hierarchical flow for predictive TCAD device simulation in DCTO applications. Using a thoroughly calibrated sub-band Boltzmann transport equation (SBTE) solver, TCAD device simulation parameters or the technology under investigation are generated automatically. This flow enables predictive accuracy of the SBTE solver at turn-around-times of SPICE simulations. It is demonstrated here for an A14 nanosheet technology, i) showing all intermediate calibration details and ii) highlighting a considerable improvement in the accuracy of ringoscillator performance.
STEM Image Based Structure Generation for Advanced CMOS Devices
Process technology computer aided design (TCAD) has become an indispensable tool to characterize proposed future technologies. However, current solutions often require tedious manual calibrations of process flows. Here, we present the automatic processing of electron microscopy (EM) images to 2D and 3D device representations. Parts of the device which are not present in the EM image are emulated to create a structure ready for device simulation. The feasibility of this approach is shown by extracting the fin shape from the EM image of a 7nm FinFET, as well as studying the impact of fin shape on device characteristics in an exemplary variability study. Additionally, the inner spacers and gate shape of a nanosheet (NS) FET are reproduced, showcasing the applicability of the presented approach to different device technologies.
A Physical TCAD Mobility Model of Amorphous In-Ga-Zn-O (a-IGZO) Devices with Spatially Varying Mobility Edges, Band-Tails, and Enhanced Low-Temperature Convergence
Amorphous indium gallium zinc oxide (a-IGZO) is becoming an increasingly important technological material. Transport in this material is conceptualized as the heavy disorder of the material causing a conduction or mobility band-edge that randomly varies and undulates in space across the entire system. Thus, transport is envisioned as being dominated by percolation physics as carriers traverse this varying band-edge landscape of “hills” and “valleys”. It is then something of a missed opportunity to model such a system using only a compact approach—despite this being the primary focus of the existing literature—as such a system can easily be faithfully reproduced as a true microscopic TCAD model with a real physically varying potential. Thus, in this work, we develop such a “microscopic” TCAD model of a-IGZO and detail a number of key aspects of its implementation. We then demonstrate that it can accurately reproduce experimental results and consider the issue of the addition of non-conducting band-tail states in a numerically efficient manner. Finally, two short studies of 3D effects are undertaken to illustrate the utility of the model: specifically, the cases of variation effects as a function of device size and as a function of surface roughness scattering.
Inflection Points in Cfet Scaling: Impact of Dtco Boosters
Complimentary FETs (CFETs) enable aggressive standard cell height (CH) reduction, facilitating on-target area scaling without shrinking contacted gate pitch (CGP). We extensively benchmark nanosheet (NS) based CFETs against gate-all-around (GAA) NSFETs using power, performance, area (PPA) as well as scalability metrics. The impact of BEoL RC, new materials, DTCO boosters is further explored. 4T CFET designed with 20 nm metal pitch (MP) offers 62% smaller area and 28% extra speed at iso-power over reference NS devices.
An Efficient and Accurate DTCO Simulation Framework for Reliability and Variability-Aware Explorations of FinFETs, Nanosheets, and Beyond
Design-Technology Co-Optimization (DTCO) emerged as pivotal driver in shaping the state-of-the-art nodes and will gain evermore importance for future technologies. This becomes most evident with the advent of complementary FETs (CFET), a technology which thrives on intricately engineered design and technology to achieve substantial boosts for both logic and memory applications. Practical DTCO implementations are realized by combination of TCAD and SPICE to achieve studies with quick turnaround times (TAT) and for seamless integration with the standard EDA design flow. Here, such a TCAD-to-SPICE DTCO flow is outlined and its application for reliability and variability-aware SRAM and RO is demonstrated.
Inflection Points in GAA NS-FET to C-FET Scaling Considering Impact of DTCO Boosters
Complimentary FETs (C-FETs) enable aggressive standard cell height reduction, facilitating on-target area scaling without shrinking contacted gate pitch (CGP). We extensively benchmark nanosheet (NS)-based C-FET s against gate-all-around (GAA) NS FETs across range of metal pitches (MPs) tracking their power, performance, and area (PPA). The impact of back-end of line (BEoL) RC, new materials, and various device boosters is further explored. Four-track C-FET designed with 20-nm MP offers 62% smaller area and provides 28% extra speed at isopower (S@P) over reference NS-FET device.
Modeling the Operation of Charge Trap Flash Memory -- Part I: The Importance of Carrier Energy Relaxation
We present a novel approach to the modeling of carrier energy relaxation during high-field phases in semiconductor-oxide-nitride-oxide-semiconductor (SONOS) flash memory gate stacks. We show that this method integrates well with TCAD simulators and that taking the energy relaxation of carriers into consideration solves two of the most prominent problems of trapping layer dynamics modeling: The missing slope degradation in incremental step-pulse programming (ISPP) simulations and the incompatibility of the resulting charge distributions with long-term room temperature charge retention measurements. This article consists of two parts where this part discusses the physical/TCAD level. The second part derives a semianalytical model specifically for programming that reduces the numerical complexity while still retaining the main physical assumptions and the applicability to experimental data.
Modeling the Operation of Charge Trap Flash Memory-Part I: The Importance of Carrier Energy Relaxation
We present a novel approach to the modeling of carrier energy relaxation during high-field phases in semiconductor-oxide-nitride-oxide-semiconductor (SONOS) flash memory gate stacks. We show that this method integrates well with TCAD simulators and that taking the energy relaxation of carriers into consideration solves two of the most prominent problems of trapping layer dynamics modeling: The missing slope degradation in incremental step-pulse programming (ISPP) simulations and the incompatibility of the resulting charge distributions with long-term room temperature charge retention measurements. This article consists of two parts where this part discusses the physical/TCAD level. The second part derives a semianalytical model specifically for programming that reduces the numerical complexity while still retaining the main physical assumptions and the applicability to experimental data.
Modeling the Operation of Charge Trap Flash Memory -- Part II: Understanding the ISPP Curve With a Semianalytical Model
Flash memory with a charge trap layer (CTL), also known as silicon-oxide-nitride-oxide-silicon (SONOS), is the most common type in production, yet there is a lack of consensus on the physical modeling of its operation. In Part I, we therefore proposed a full TCAD model based on an energy relaxation approach and showed that it captures experimentally observed memory operation. This numerical model, however, comes with considerable complexity and computational cost. In Part II, we therefore construct a semianalytical model based on similar physical assumptions, called Pheido, to be as simple as possible. We first derive the model equations based on a balance of current densities, detailing the approximations made. We then use Pheido to analyze the various regimes of an experimental incremental step pulse programming (ISPP) curve and compare it to the full TCAD model derived in Part I. Finally, we investigate the impact of material and structural cell parameters on the ISPP curve, illustrating how the Pheido model offers wide utility at low computational cost.
Identifying Defects in Charge Trapping Related Phenomena
Charge trapping at oxide defects is a prevalent phenomenon in most modern nanoelectronic devices, leading to detrimental reliability issues like bias temperature instability (BTI), trap-assisted tunneling (TAT) or random telegraph noise (RTN). Although these effects are clearly visible in experiments, the microscopic nature of the involved defects remains elusive. However, an in-depth understanding of the underlying atomistic processes and defects responsible for device degradation is key to further improve device reliability. In this work we discuss how insights gained from electrical characterization methods, ab-initio calculations based on density functional theory (DFT), and compact device models can be combined to identify defects near the semiconductor/oxide interface which compromise device reliability.
A Study of the Variability and Design Considerations of Ferroelectric VNAND Memories With Polycrystalline Films Using An Experimentally Validated TCAD Model
In this work a TCAD model of a ferroelectric VNAND device is developed and validated against experimental data. After its accuracy is demonstrated it is then used to explore a number of issues related to the future potential of such devices including: the expected performance if negative trapping effects are reduced, the variability issues created by the polyphasic nature of hafnium-based ferroelectric films, the issue of the destructive nature of the read sweep, and poor effect of ERS pulses. In addition, some mitigation strategies to combat these issues are briefly discussed.
Comphy v3.0 -- A compact-physics framework for modeling charge trapping related reliability phenomena in MOS devices
Charge trapping plays an important role for the reliability of electronic devices and manifests itself in various phenomena like bias temperature instability (BTI), random telegraph noise (RTN), hysteresis or trap-assisted tunneling (TAT). In this work we present Comphy v3.0, an open source physical framework for modeling these effects in a unified fashion using nonradiative multiphonon theory on a one-dimensional device geometry. Here we give an overview about the underlying theory, discuss newly introduced features compared to the original Comphy framework and also review recent advances in reliability physics enabled by these new features. The usefulness of Comphy v3.0 for the reliability community is highlighted by several practical examples including automatic extraction of defect distributions, modeling of TAT in high- capacitors and BTI/RTN modeling at cryogenic temperatures.
Process Simulation in Micro- and Nano-Electronics
The continued transistor miniaturization, the introduction of novel materials and geometries in complementary semiconductor-metal-oxide (CMOS) fabrication, and the ever-increasing complexity of the processes required for modern integrated circuits (ICs) must be supported by proper process- and device-technology computer aided design (TCAD) tools. Improvements in performance, power efficiency, and area density (PPA) from one technology node to the next nowadays involves substantial architectural and material innovations through TCAD-supported design-technology co-optimization (DTCO).
Oxide and Interface Defect Analysis of lateral 4H-SiC MOSFETs through CV Characterization and TCAD Simulations
We investigated oxide and interface defects of lateral 4H-SiC MOSFETs through capacitance-voltage (C-V) and conductance-voltage (G-V) characterization at various frequencies and temperatures. By employing consecutive up and down sweeps of the gate voltage at three different temperatures, we experimentally characterized the hysteresis width as the difference between up and down sweeps in the depletion to accumulation (d-a) and depletion to inversion (d-i) regions. We observed an increase in the hysteresis width with decreasing temperature. Although the hysteresis width is not affected by the small-signal frequency, at the same time, increasing the frequency leads to a strong stretch-out effect, especially in the d-i region.Our measurement results indicate that the hysteresis deformation of the C-V curves is dominated by three different trap types. First, interface acceptor-like defects located close to the conduction band can follow the small-signal frequency. Slower acceptor-like border traps with trap levels both close to the conduction band and in the middle of the band gap are however responsible for the increase of trapped negative charge with increasing gate voltage. Finally, we assume the presence of a fixed positive charge.
Effect of Mask Geometry Variation on Plasma Etching Profiles
It is becoming quite evident that, when it comes to the further scaling of advanced node transistors, increasing the flash memory storage capacity, and enabling the on-chip integration of multiple functionalities, “there’s plenty of room at the top”. The fabrication of vertical, three-dimensional features as enablers of these advanced technologies in semiconductor devices is commonly achieved using plasma etching. Of the available plasma chemistries, SF6/O2 is one of the most frequently applied. Therefore, having a predictive model for this process is indispensable in the design cycle of semiconductor devices. In this work, we implement a physical SF6/O2 plasma etching model which is based on Langmuir adsorption and is calibrated and validated to published equipment parameters. The model is implemented in a broadly applicable in-house process simulator ViennaPS, which includes Monte Carlo ray tracing and a level set-based surface description. We then use the model to study the impact of the mask geometry on the feature profile, when etching through circular and rectangular mask openings. The resulting dimensions of a cylindrical hole or trench can vary greatly due to variations in mask properties, such as its etch rate, taper angle, faceting, and thickness. The peak depth for both the etched cylindrical hole and trench occurs when the mask is tapered at about 0.5°, and this peak shifts towards higher angles in the case of high passivation effects during the etch. The minimum bowing occurs at the peak depth, and it increases with an increasing taper angle. For thin-mask faceting, it is observed that the maximum depth increases with an increasing taper angle, without a significant variation between thin masks. Bowing is observed to be at a maximum when the mask taper angle is between 15° and 20°. Finally, the mask etch rate variation, describing the etching of different mask materials, shows that, when a significant portion of the mask is etched away, there is a notable increase in vertical etching and a decrease in bowing. Ultimately, the implemented model and framework are useful for providing a guideline for mask design rules.
DTCO flow for air spacer generation and its impact on power and performance at N7
A novel DTCO flow is described with the principal aim to study the impact of air spacer fabrication on the power and performance of a 5-stage inverter ring oscillator at the 7 nm node. The flow incorporates physical and analytical process models from TU Vienna's ViennaPS simulation tool together with device and circuit simulations from GTS Framework’s Cell Designer. The air spacer is usually filled by sequential conformal and non-conformal deposition steps. The impact of the thickness of the conformal layer and the sticking probability during non-conformal deposition on the ring oscillator performance is studied here. The air gap, which forms the core of the air spacer, is generated during the non-conformal deposition step. We extract the relative effective permittivity of the air spacer as a function of these two fabrication parameters by solving the Poisson equation to obtain the spacer capacitance. Finally, SPICE model cards are extracted automatically from the TCAD transistor characteristics and the parasitic network is calculated from the full 3D ring oscillator logic cell using a field solver.
Quasi-Fermi-Based Charge Transport Scheme for Device Simulation in Cryogenic, Wide Bandgap, and High-Voltage Applications
We present a novel approach to solving the transport problem in semiconductors. We reformulate the drift-diffusion (DD) equations in terms of the quasi-Fermi-energies as solution variables; a drastic increase in numerical stability is achieved, which permits the simulation of devices at cryogenic temperatures as well as wide bandgap devices using double precision arithmetic, instead of extended precision arithmetic which would otherwise be required to solve these applications using regular DD.
Performance and Variability-Aware SRAM Design for Gate-All-Around Nanosheets and Benchmark with FinFETs at 3nm Technology Node
For the 3nm technology node, horizontal gate-all- around nanosheet devices offer a non-disruptive process tran- sition from fin technologies with the advantage of full 3D design flexibility and better short-channel control. For SRAM cell design, this enables non-digital n/pFET balancing. In this paper, a performance and variability-aware DTCO flow is used to benchmark nanosheet SRAM cells against fin technologies at 3nm node, targeted at 45 nm CPP and 21 nm MP. The impact of gate length, fin height, number of nanosheets, effective n/pFET widths, channel doping, and vertical nanosheet pitch is studied. Despite the lower parasitic capacitances of fins, the design freedoms of nanosheets enable superior SRAM operation in terms of both Vmin and read delay even at smaller cell areas.
Monolithic TCAD Simulation of Phase-Change Memory (PCM/PRAM) + Ovonic Threshold Switch (OTS) Selector Device
Owing to the increasing interest in the commercialization of phase-change memory (PCM) devices, a number of TCAD models have been developed for their simulation. These models formulate the melting, amorphization and crystallization of phase-change materials as well as their extreme conductivity dependence on both electric field and temperature into a set of self-consistently-solved thermoelectric and phase-field partial-differential equations. However, demonstrations of the ability of such models to match actual experimental results are rare. In addition, such PCM devices also require a so-called selector device - such as an Ovonic Threshold Switching (OTS) device - in series for proper memory operation. However, monolithic simulation of both the PCM and OTS selector device in a single simulation is largely absent from the literature, despite its potential value for material- and design-space explorations. It is the goal of this work to first characterize a PCM device in isolation against experimental data, then to demonstrate the qualitative behavior of a simulated OTS device in isolation and finally to perform a single monolithic simulation of the PCM + OTS device within the confines of a commercially available TCAD solver: GTS Framework.
On the feasibility of DoS-engineering for achieving sub-60 mV subthreshold slope in MOSFETs
We present the operating principle of an ideal Cold Source Field Effect Transistor and check the DoS source engineering impact on its subthreshold slope. The Subband Boltzmann Transport Equation is solved and the resulting transfer curves in the ballistic regime are presented, as well as those including the effects of scattering. The inclusion of scattering reveals its importance in the rethermalization of the cold carriers at the source extension and the degradation in the static leakage of the device. Finally, we show the impact in the SS when substituting the semiconducting source extension by the cold metal.
Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors
Vertical Nanowire Junction-less Transistors (VN-WFET) are a promising technology for designing energy-efficient neural networks. This work presents the first results for 3D VNWFET logic cell design taking into account the influence of intra-cell parasitic interconnects on circuit performances. The proposed methodology is used to investigate the performance of a CMOS inverter through co-simulation of the VNWFET SPICE compact model coupled with the circuit parasitic netlist extracted from 3D TCAD simulations using a standard circuit simulator.
A Novel Approach to Modeling Insulator Wave-Function Penetration and Interface Roughness Scattering in MOSFETs
We present novel models for insulator wave-function penetration and for interface roughness scattering. We review the intricate relationship between modeling of these two effects, with respect to usability, computational effort, and numerical stability. We demonstrate that our novel approach is capable of remedying all of the common issues of previous approaches at no additional computational cost.
Circuit Design Flow dedicated to 3D vertical nanowire FET
To continue transistor downscaling beyond lateral 7nm devices, gate-all-around (GAA) junction-less vertical nanowire field effect transistors (VNWFET) represent a promising option. This invited paper presents the circuit design flow based on a vertical junctionless transistor technology. On the basis of state-of-the-art junctionless nanowire transistors (JLNT), DC characterization, compact modelling, EM simulation and parameter extraction are described in details. Using this circuit design flow, a set of innovative 3D circuit architectures are explored.
Optimization and Benchmarking FinFETs and GAA Nanosheet Architectures at 3-nm Technology Node: Impact of Unique Boosters
Using a full design-technology cooptimization (DTCO) framework, we benchmark gate-all-around (GAA) nanosheet (NS) FETs against FinFETs at 3-nm logic technology relevant dimensions. First, to understand the intrinsic gain from NS, both device architectures are simulated using fixed technology ground rules [contact poly pitch (CPP), metal pitch $M_x$ , and cell height] and process assumptions (PAs), including stress, doping, junctions, and oxide thickness. Full geometry optimization along the CPP direction (gate length $L_ ext G$ , spacer thickness $T_ ext SP$ , and contact length $L_ ext CNT$ ) is done to self-consistently account for tradeoff between short-channel effects (SCE), intrinsic and extrinsic resistances, and capacitances (device and parasitic). This leads to independent optimum design specifications for each Fin and NS architectures. Impact of Fin tapering and NS width and stack number are further investigated, showing additional design flexibility of GAA NS devices at scaled dimensions.
On the Modeling of Polycrystalline Ferroelectric Thin Films: Landau-Based Models Versus Monte Carlo-Based Models Versus Experiment
Due to the potential for technological application, there has been an explosion of interest in heavily polycrystalline ferroelectric nanofilms, such as those of doped hafnium oxide. However, the heavily polycrystalline nature of these materials invalidates conventional model- ing approaches as the dynamics have been found to be: 1) nucleation-limited; 2) involve grains of ferroelectric material interspersed among grains of alternative, nonferroelectric material; and 3) the direct interaction between these grains is observed to be minimal. In this article, we con- sider seven separate compact or "0-D" models of such polycrystalline films. Four of these models are based on a Landau paradigm and two are based on a Monte Carlo (MC) paradigm. The seventh is the traditional Preisach model. Although all of these models have been used in the literature to model novel polycrystalline ferroelectric nanofilms, here we compare and contrast the accuracy and physical appro- priateness of each model by comparing both their static and dynamic properties against experimental data. We then find that although all models except single-grain models are capable of reproducing the static properties, only the MC models replicate the long-time dynamical properties. Thus, it is demonstrated that not all models are equally valid for the accurate modeling of such films.
TCAD Modeling of Temperature Activation of the Hysteresis Characteristics of Lateral 4H-SiC MOSFETs
We investigate the temperature dependence of the hysteresis in the transfer characteristics of 4H silicon carbide (4H-SiC) lateral MOSFETs. Within temperatures ranging from 150 to 300 K, we experimentally characterize the hysteresis width as the difference of the threshold voltage between up and down sweeps. We observe a considerable increase in the hysteresis width toward lower temperatures. When the gate voltage sweeps up, the threshold voltage shifts toward positive gate voltages. This shift is maintained even during the subsequent down sweep. We attribute this behavior to acceptor-like border traps, which get more negatively charged at higher gate voltages. These traps are presumably located near the SiC/SiO2 interface with energy levels close to the SiC conduction band edge. Using a two-state non-radiative multi-phonon model, we calculated capture and emission times to show that the hysteresis width corresponds to the charge stored on these traps and, hence, possesses an intrinsic temperature dependence due to the transition barriers.
Trap-polarization interaction during low-field trap characterization on hafnia-based ferroelectric gatestacks
This paper investigates the characterization of charge trapping and its modelling on hafnia-based ferroelectric field effect transistors (FeFETs). Defect characterization on MOSFETs can be done by studying threshold voltage shifts (∆Vth) as a function of charging and relaxation times. At positive gate voltages one expects electron trapping in the gate oxide to result in a positive shift of the threshold voltage (Vth). However, on a FeFET those conditions will induce polarization changes in the gate oxide leading to a negative Vth-shift, complicating the characterization of defect levels. We aim to alleviate these difficulties by modelling the polarization and trapping in FeFETs over a wide range of timescales, suitable for defect characterization. We demonstrate quantitative agreement on long timescales with a static polarization model, while a time-dependent polarization model can be used for qualitative agreement over a wide range of times from 30 ms to 2 ks.
Understanding the ISPP Slope in Charge Trap Flash Memory and its Impact on 3-D NAND Scaling
We present a physical modeling approach that explains the non-ideal ISPP slope in charge trap layer (CTL) flash memory and its impact on 3-D NAND vertical pitch scaling. First, we derive an expression for the VT change rate and use its field dependence to reproduce experimental vertical NAND ISPP slopes. Next, we implement a 2.5-D TCAD model based on these insights and show significant program voltage increase (>5V) in realistic 3-D NAND flash devices with scaling vertical pitch (down to 10nm). Finally, we evaluate high-k CTL and airgaps as mitigation measures at scaled pitch.
Understanding the ISPP Slope in Charge Trap Flash Memory and its Impact on 3-D NAND Scaling
We present a physical modeling approach that explains the non-ideal ISPP slope in charge trap layer (CTL) flash memory and its impact on 3-D NAND vertical pitch scaling. First, we derive an expression for the VT change rate and use its field dependence to reproduce experimental vertical NAND ISPP slopes. Next, we implement a 2.5-D TCAD model based on these insights and show significant program voltage increase (>5V) in realistic 3-D NAND flash devices with scaling vertical pitch (down to 10nm). Finally, we evaluate high-k CTL and airgaps as mitigation measures at scaled pitch.
Nano Device Simulator—A Practical Subband-BTE Solver for Path-Finding and DTCO
We present an in-depth discussion on the subband Boltzmann transport (SBTE) methodology, its evolution, and its application to the simulation of nanoscale MOSFETs. The evolution of the method is presented from the point of view of developing a commercial general-purpose SBTE solver, the GTS nano device simulator (NDS). We show a wide range of applications SBTE is suited for, including state-of-the-art nonplanar and well-established planar technologies. It is demonstrated how SBTE can be employed both as a path-finding tool and a fundamental component in a DTCO-flow.
Variability-Aware DTCO Flow: Projections to N3 FinFET and Nanosheet 6T SRAM
Variability increases with downscaling, making it a vital component in the assessment of upcoming technologies. We use a variability-aware DTCO flow, which seamlessly integrates accurate TCAD simulations with industry-proven SPICE solutions. The impact of local variability sources on SRAM KPIs is analyzed for N3 FinFET and nanosheet technologies. Assuming typical process parameters, the geometrical variations due to LWR, STI recess, and epitaxial growth significantly affect the SRAM variability. However, the main contributor to variability for N3 technologies is MGG, highlighting the crucial role of metal grains size reduction for technology optimization.
Variability-Aware DTCO Flow: Projections to N3 FinFET and Nanosheet 6T SRAM
Variability increases with downscaling, making it a vital component in the assessment of upcoming technologies. We use a variability-aware DTCO flow, which seamlessly integrates accurate TCAD simulations with industry-proven SPICE solutions. The impact of local variability sources on SRAM KPIs is analyzed for N3 FinFET and nanosheet technologies. Assuming typical process parameters, the geometrical variations due to LWR, STI recess, and epitaxial growth significantly affect the SRAM variability. However, the main contributor to variability for N3 technologies is MGG, highlighting the crucial role of metal grains size reduction for technology optimization.
A Unified Physical BTI Compact Model in Variability-Aware DTCO Flow: Device Characterization and Circuit Evaluation on Reliability of Scaling Technology Nodes
We developed a unified physical and statistical compact model of Bias Temperature Instability (BTI) effects on scaling technology nodes towards robust VLSI design, with an excessive amount of complex stress/recovery pattern characterization, ultralong-term aging prediction, and technology of statistical variability (TSV) analysis, realizing cycle-to-cycle/device-to-device reliability evaluations. This model is based on a 2/4-state Defect-Centric (DC) theory and verified by TCAD simulation, providing a deep insight into the properties of the defects (e.g., energy level distribution, occupancy probability etc.). By calibration to Fin-FET experiments (of down to 14 nm node), it is successfully implemented into BSIM-CMG for analysis of dynamic time evolutionary and dynamic voltage scaling. This physics-, variablity-, and tolerance-aware model has the potential to boost the design technology co-optimization (DTCO) flow of reliability in VLSI to the next generation of technology nodes.
A TCAD Compatible SONOS Trapping Layer Model for Accurate Programming Dynamics
We present a TCAD model for the accurate de- scription of charging kinetics of trapping layers in 3D gate-all- around VNAND SONOS devices. We build on the established description of the trapping layer as trap-rich semiconductor and show that a strongly field-dependent carrier mobility greatly improves the reproduction of experimental incremental step pulse programming (ISPP) slopes. The resulting model was implemented in a commercial TCAD simulator and shown to accurately predict ISPP and retention loss measurement data with one consistent parameter set.
1.5-nm Node Surrounding Gate Transistor (SGT)-SRAM Cell with Staggered Pillar and Self-Aligned Process for Gate, Bottom Contact, and Pillar
We propose the architecture and manufacturing process of 6 surrounding-gate-transistor (SGT) SRAM cell for the 1.5nm technology node. The staggered layout and self-aligned patternings have successfully realized a transition from 5nm to 1.5nm node with the same SGT diameter. Electrical characteristics by TCAD simulation are finally demonstrated.
A TCAD Compatible SONOS Trapping Layer Model for Accurate Programming Dynamics
We present a TCAD model for the accurate description of charging kinetics of trapping layers in 3D gate-all-around VNAND SONOS devices. We build on the established description of the trapping layer as trap-rich semiconductor and show that a strongly field-dependent carrier mobility greatly improves the reproduction of experimental incremental step pulse programming (ISPP) slopes. The resulting model was implemented in a commercial TCAD simulator and shown to accurately predict ISPP and retention loss measurement data with one consistent parameter set.
Reliability and Variability-Aware DTCO Flow: Demonstration of Projections to N3 FinFET and Nanosheet Technologies
Reliability and variability-aware simulations of logic cells are essential to correctly analyze and predict the performance of upcoming technologies. A simulation flow for DTCO is presented here, which combines the accuracy of TCAD with the performance of SPICE - utilizing parasitic extractions, the impedance field method for variations, and the compact-physics simulator comphy for reliability. Good agreement with experimental RO performance of N14 is demonstrated and projections to N3 FinFET and nanosheet technologies are made.
Performance and Leakage Analysis of Si and Ge NWFETs Using a Combined Subband BTE and WKB Approach
We are the first to present a subband-BTE solver with a fully integrated source/drain-tunneling current calculation based on the WKB-approximation. The method is validated against ballistic NEGF calculations showing good agreement. An investigation of Si and Ge-based NWFETs is performed showing that intra-band source/drain-tunneling is not a concern for Si devices. For Ge-based PMOS devices however, tunneling leakage limits sensible LG -scaling to around 20 nm.
Modeling the Hysteresis of Current-Voltage Characteristics in 4H-SiC Transistors
4H-SiC MOSFETs exhibit a hysteresis of the transfer characteristics due to electrically active traps near the SiC/SiO2 interface. Our measurements, conducted within the temperature range of 150-260 K revealed an interesting behavior, namely a notable decreasing hysteresis width towards higher T. During the up-sweep of gate voltage Vgs curves are shifted towards higher gate voltages compared to the curves acquired at the down-sweep of Vgs. This implies that more traps are negatively charged at higher Vgs conditions, and we attribute this behavior to acceptor-like border traps in oxide having its charge transition level 0/-1 near the SiC conduction band edge. To model electron capture and emission events of these oxide traps, we use the non-radiative multiphonon model. We calculate the capture and the emission times. The temperature dependence of the latter is the dominant feature which decreases the hysteresis width with increasing T. Our modeling approach is capable of reproducing the hysteresis width over the measured T range with good accuracy.
Mixed Hot-Carrier/Bias Temperature Instability Degradation Regimes in Full VG, VD Bias Space: Implications and Peculiarities
Characterizing mixed hot-carrier/bias temperature instability (BTI) degradation in full VG, VD bias space is a challenging task. Therefore, studies usually focus on individual degradation mechanisms, such as BTI and hot-carrier degradation (HCD). However, a simple superposition of these mechanisms at an arbitrary VG, VD combination often fails to predict the cumulative damage. We experimentally acquired a large data set covering the full bias space of a pMOSFET which allows us to obtain detailed degradation and recovery maps. Our models for describing oxide and interface defects provide physical insights into the underlying mechanisms and a possible interplay between the degradation modes. Additionally, we perform a dedicated experiment to reveal the implications of different stress regimes onto the various types of defects by switching BTI and HCD stress conditions.The results clearly reveal the conceptual limits of the assumption of independent degradation regimes.
Semi-Automated Extraction of the Distribution of Single Defects for nMOS Transistors
Miniaturization of metal-oxide-semiconductor field effect transistors (MOSFETs) is typically beneficial for their operating characteristics, such as switching speed and power consumption, but at the same time miniaturization also leads to increased variability among nominally identical devices. Adverse effects due to oxide traps in particular become a serious issue for device performance and reliability. While the average number of defects per device is lower for scaled devices, the impact of the oxide defects is significantly more pronounced than in large area transistors. This combination enables the investigation of charge transitions of single defects. In this study, we perform random telegraph noise (RTN) measurements on about 300 devices to statistically characterize oxide defects in a Si/SiO2 technology. To extract the noise parameters from the measurements, we make use of the Canny edge detector. From the data, we obtain distributions of the step heights of defects, i.e., their impact on the threshold voltage of the devices. Detailed measurements of a subset of the defects further allow us to extract their vertical position in the oxide and their trap level using both analytical estimations and full numerical simulations. Contrary to published literature data, we observe a bimodal distribution of step heights, while the extracted distribution of trap levels agrees well with recent studies.
Physical Modeling of Bias Temperature Instabilities in SiC MOSFETs
Transistors fabricated on SiC substrates show superior properties for their application in high-power electronics. However, the performance of SiC MOSFETs in general can still not be completely exploited yet due to a higher defect density compared to Si/SiO2 based devices. The defects give rise to a distinct hysteresis in the transfer characteristics and increased drifts of the threshold voltage over time, i.e. bias temperature instabilities, making accurate time-to-failure analysis more challenging. In our work we carefully analyze lateral channel SiC MOSFETs utilizing measure-stress-measure (MSM) schemes. To explain the experimental data we perform physics based device simulations considering the impact of a large set of single defects employing a two-state non-radiative multiphonon defect model. This approach allows us to extract defect bands for electron and hole trapping and to link them to possible defect structures proposed in the literature. Additionally, we compare simulation results employing our extracted trap bands with MSM data measured on vertical channel devices. Finally, an accurate lifetime prediction at operating conditions is presented.
From Gate Oxide Characterization to TCAD Predictions: Exploring Impact of Defects Across Technologies
Despite extensive modeling efforts, not all semiconductor fabrication processes are fully understood on a physical level and phenomenological tools are used to analyze process splits. This works well for incremental improvements but has limitations when it comes to more fundamental developments. TCAD simulators, on the other hand, offer physical models and consider non-homogeneous field distributions and the effect of discrete charges. However, they are considerably more complex to use and to parametrize which can make them impractical. Therefore, the efficient gate stack simulator Comphy was presented recently which is used to extract physical defect properties. In this work, a development strategy is presented which employs this extraction methodology followed by an import of the defect parameters in a TCAD simulator. Using the same gate stack on different geometries we study the degradation and time dependent variability which increases from planar MOSFETs to FinFETs and is even worse for nanowires.
Transport of Charge Carriers along Dislocations in Si and Ge
Experimental observations and quantum mechanical device simulations point to different electronic properties of dislocations in silicon and germanium. The experimental data suggest a supermetallic behavior of the dislocations in Si and thus the high strain in the dislocation core is thought to cause the confinement of the charge carriers, which leads to the formation of a 1D electron gas along a dislocation (quantum wire). The resulting significant increase in the electron concentration corresponds to a marked increase in the drain current of metal–oxide–semiconductor field-effect transistor (MOSFET). The specific resistance of an individual dislocation in Ge is about nine orders of magnitude higher than for a dislocation in Si. The experimental measurements of the strain in dislocation cores in Ge are still missing. Based on the band structure data, the generation of a strain equivalent to that of the dislocation cores in Si appears to be very challenging because of the transition from an indirect into a direct semiconductor with about tenfold lower strain levels. The lower strain in the dislocation core in germanium may not support the carrier confinement as proposed for the dislocation core of silicon, and consequently 1D electron gases are not expected to form along the dislocations in Ge.
Full (Vg, Vd) Bias Space Modeling of Hot-Carrier Degradation in Nanowire FETs
Simulations of hot-carrier degradation of nanowire field-effect transistors are reported. The simulations rely on the carrier energy distribution function, obtained by solving the Boltzmann transport equation. To model the contribution of impact ionization, the hydrodynamic scheme is employed. A range of pertinent physical mechanisms is invoked and discussed to adequately reproduce HCD measurements in the full (Vg, Vd) bias space. Impact ionization is discussed as an important ingredient of HCD at low gate, high drain voltages.
On the Characterization and Separation of Trapping and Ferroelectric Behavior in HfZrO FET
$N$ -channel FETs with ferroelectric (FE) HfZrO gate oxide are fabricated, showing steep subthreshold slope under certain conditions. Possible origins of $I _D$ – $V _G$ hysteresis, the hysteresis versus subthreshold slope tradeoff, dependence on the bias voltage and temperature and the competition between trapping and FE behavior are reported and discussed. A band of active traps in the FE layer responsible for charge trapping during device operation is characterized. Transient $I _D$ – $V _G$ measurements are introduced to facilitate differentiating between trapping and FE behavior during subthreshold slope measurements.
Impact of Mixed Negative Bias Temperature Instability and Hot Carrier Stress on MOSFET Characteristics—Part II: Theory
In this paper, we examine the interplay of two serious reliability issues in MOSFET devices, namely, bias temperature instability (BTI) and hot-carrier degradation (HCD). Most publications are devoted to the characterization of either BTI or HCD, and complex models have been developed to independently describe each degradation mode. However, very limited data are available on the interplay of both degradation regimes, particularly the effect of a drain bias onto the charging and discharging dynamics of oxide traps. Part I of this paper provides an extensive experimental study toward the impact of mixed-mode stress conditions on the dynamics of oxide defects. Here, we present the first microscopic modeling approach beyond a simple electrostatic approximation. We extend the existing nonradiative multiphonon theory by taking nonequilibrium processes such as full carrier distribution functions which include the effect impact ionization along the channel into account. To ultimately validate our framework, we compare simulation results and experimental data for a single-oxide defect as well as a large ensemble of traps in a MOSFET device. We show that our modeling approach accurately captures the rather puzzling measurement trends for a broad stress regime and allows developing the knowledge on how oxide defects can be affected by an increased drain stress.
Distribution Function Based Simulations of Hot-Carrier Degradation in Nanowire FETs
Hot-carrier degradation (HCD) is again becoming a growing VLSI reliability problem. This work reports hot-carrier simulations for Si nanowire field-effect transistors (NW FETs) based on the carrier energy distribution function (DF) and compares the results to measured data. The importance of impact ionization for HCD simulations is discussed. A 1-to-1 relation between the extent of interface defects generated by hot-carriers in the channel and the degradation of several FET parameters is observed.
Cell Designer – a Comprehensive TCAD-Based Framework for DTCO of Standard Logic Cells
We present the first practical TCAD-based work flow for design-technology co-optimization (DTCO) of standard cells. The flow consists of parametric cell layout templates, layout-based structure generation, mixed-mode transient electri- cal device simulation, and data collection and analysis. Based on electrical and structural characterizations of the iN14, iN10, and iN7 nodes, the models presented in this work feature a projection for 5nm technology nodes based on FinFET, nanowire, and nanosheet. Transient five-stage ring-oscillator simulations show a clear advantage for the FinFET in terms of switching frequency and power consumption.
The Impact of Parasitic Capacitances on NCFET Performance – a TCAD Study
We investigate the effectiveness of the performance boost provided through ferro-electric materials in negative-capacitance FETs (NCFETs) using a hybrid TCAD/compact modeling approach. We show that, in a practical device, the performance boost is dominated by parasitic capacitances. The impact of the doping profile on NCFET performance is studied showing that tight control of the doping is required to maintain the boost in highly scaled devices.
A Physical Model for the Hysteresis in MoS extsubscript2 Transistors
Even though the hysteresis in the gate transfer characteristics of two-dimensional (2D) transistors is a frequently encountered phenomenon, the physics behind it are up to now only barely understood, let alone modeled. Here, we demonstrate that the hysteresis phenomenon can be captured accurately by a previously established non-radiative multiphonon model describing charge capture and emission events in the surrounding dielectrics. The charge transfer model is embedded into a drift-diffusion based TCAD simulation environment, which was adapted to 2D devices. Our modeling setup was validated against measurement data on a back-gated single-layer MoS2 transistor with SiO2 as a gate dielectric. We use the modeling approach to gain a thorough understanding of the hysteresis, which will help to control this problem in future devices.
Comphy — A Compact-Physics Framework for Unified Modeling of BTI
Metal-oxide-semiconductor (MOS) devices are affected by generation, transformation, and charging of oxide and interface defects. Despite 50 years of research, the defect structures and the generation mechanisms are not fully understood. Most light has been shed onto the charging mechanisms of pre-existing oxide defects by using the non-radiative multi-phonon theory. In this work we present how the gist of physical models for pre-existing oxide defects can be efficiently abstracted at a minimal loss of physical foundation and accuracy. Together with a semi-empirical model for the generation and transformation of defects we establish a reaction-limited framework for unified simulation of bias temperature instabilities (BTI). The applications of the framework we present here cover simulation of BTI for negative (NBTI) and positive (PBTI) gate voltages, life time extrapolation, AC stress with arbitrary signals and duty cycles, and gate stack engineering.
Scaling FDSOI Technology down to 7 nm – a Physical Modeling Study Based on 3D Phase-Space Subband Boltzmann Transport
We present the first truly full-band approach to solving the subband Boltzmann transport (SBTE) equation in three-dimensional phase space. The solution is applied to investigate the evolution of the FDSOI MOSFET towards the 7nm node. Our findings show that single-gate FDSOI technology can be effectively scaled down to the 14 nm node, because the on-current gains are large enough to offset the SS-degradation. Beyond 14 nm a double-gate thin-body geometry is required to maintain electrostatic control.
Characterization and physical modeling of the temporal evolution of near-interfacial states resulting from NBTI/PBTI stress in nMOS/pMOS transistors
The last decade of BTI research has seen a frantic search for ultra-fast measurement methods to correctly understand the impact of fast as-grown traps which impact the initial phase (1 ks) of the degradation and recovery. These methods focus mostly on determining the time-dependence of the threshold voltage shift. Other experimental methods able to resolve the energetic distribution of traps in the bandgap have recently not been as frequently employed as they introduce a large delay and also require switching the device into accumulation, which considerably accelerates recovery. Here we use detailed CV measurements to study NBTI/PBTI in SiO2 nMOS/pMOS capacitors. We extract a unique defect band inside the SiO2 insulator which can describe the build-up of near-interfacial states over time in all four combinations using our recently suggested gate-sided hydrogen release model. Our results suggest that depending on the transistor type and stress bias conditions, the generated slowly-recovering near-interfacial states are due to a combination of slower oxide traps and faster Pb centers.
Characterization and physical modeling of the temporal evolution of near-interfacial states resulting from NBTI/PBTI stress in nMOS/pMOS transistors
The last decade of BTI research has seen a frantic search for ultra-fast measurement methods to correctly understand the impact of fast as-grown traps which impact the initial phase (1 ks) of the degradation and recovery. These methods focus mostly on determining the time-dependence of the threshold voltage shift. Other experimental methods able to resolve the energetic distribution of traps in the bandgap have recently not been as frequently employed as they introduce a large delay and also require switching the device into accumulation, which considerably accelerates recovery. Here we use detailed CV measurements to study NBTI/PBTI in SiO2 nMOS/pMOS capacitors. We extract a unique defect band inside the SiO2 insulator which can describe the build-up of near-interfacial states over time in all four combinations using our recently suggested gate-sided hydrogen release model. Our results suggest that depending on the transistor type and stress bias conditions, the generated slowly-recovering near-interfacial states are due to a combination of slower oxide traps and faster Pb centers.
Physical modeling of the hysteresis in M0S2 transistors
The hysteresis in the gate transfer characteristics of transistors made of two-dimensional materials is one of the most obvious problems of this novel technology. Here we attempt for the first time to develop a physical modeling approach for describing this hysteresis in devices based on two-dimensional materials. Our model is based on a drift-diffusion TCAD simulation coupled to a previously established non-radiative multiphonon model for describing charge capture and emission events in the surrounding dielectrics, which are considered the main cause for the observed hysteresis. We validate our model against measurement data on a back-gated single-layer MoS2 transistor with SiO2 as a gate dielectric. Our study provides new insights into the physical reasons for the observed hysteresis, thereby leading the way towards an alleviation of this problem in future devices.
Towards Physics-Based DTCO for Performance of Advanced Technology Nodes
We present a case study which shows the path towards design-technology co-optimization (DTCO) based on physical device modeling as opposed to simulation based on empirical mobility models. This allows for more accurate and robust predictions of device performance, and allows to assess novel process options found in 7 nm and 5 nm technology nodes. A more than ten-fold increase in computational efficiency brings turn-around times down sufficiently to make physical models suitable for the DTCO process.
TCAD-Based Characterization of Logic Cells: Power, Performance, Area, and Variability
We present a novel approach for extracting the power-performance-area PPA parameter and their variability directly from a TCAD model of a logic cell. The process involves layout-based structure generation based on technology description files, transient device simulation, and parameter extraction of timing delays and power consumption. Different sources of global and local variability can be added to investigate the sensitivity of timing and power parameters. The entire process is quick and fully automated from GDSII file to PPA characteristics, and is thus suitable for use by cell and circuit designers. The extracted parameters and statistics can be directly used in high-level descriptions of digital circuits and systems.
TCAD-based characterization of logic cells: Power, performance, area, and variability
We present a novel approach for extracting the power-performance-area PPA parameter and their variability directly from a TCAD model of a logic cell. The process involves layout-based structure generation based on technology description files, transient device simulation, and parameter extraction of timing delays and power consumption. Different sources of global and local variability can be added to investigate the sensitivity of timing and power parameters. The entire process is quick and fully automated from GDSII file to PPA characteristics, and is thus suitable for use by cell and circuit designers. The extracted parameters and statistics can be directly used in high-level descriptions of digital circuits and systems.
BTI reliability and time-dependent variability of stacked gate-all-around Si nanowire transistors
We report experimental results of the N/PBTl (Negative/Positive Bias Temperature Instability) reliability of vertically stacked Gate-All-Around (GAA) silicon nanowire (NW) MOSFETs. We benchmark the lifetime of these novel devices against FinFETs with different widths and similar gate-stack. We do not only compare the average degradation, but also the time-dependent variability. At last, we predict the impact of the nanowire diameter on the reliability using TCAD simulations. Both the experimental results and the simulations indicate that BTI reliability is not negatively impacted down to a nanowire diameter of 6nm.
Impact of Defect‐Induced Strain on Device Properties
A significant increase of the drain current appears if defined arrangements of dislocations are present in the channel of MOSFETs. Furthermore, analyses of the electronic properties of individual defects refer to a supermetallic behavior of dislocations. The reason is the extremely high strain in the dislocation core exceeding values of ϵ ≅ 0.1. Such high strain causes substantial changes of the band structure and means that dislocations represent quantum wires. Quantum mechanical device simulations based on this conclusion demonstrated the transport of carriers on dislocations. The effect of gate voltage and strain in the dislocation core was analyzed in detail.
Impact of Defect‐Induced Strain on Device Properties
A significant increase of the drain current appears if defined arrangements of dislocations are present in the channel of MOSFETs. Furthermore, analyses of the electronic properties of individual defects refer to a supermetallic behavior of dislocations. The reason is the extremely high strain in the dislocation core exceeding values of ϵ ≅ 0.1. Such high strain causes substantial changes of the band structure and means that dislocations represent quantum wires. Quantum mechanical device simulations based on this conclusion demonstrated the transport of carriers on dislocations. The effect of gate voltage and strain in the dislocation core was analyzed in detail.
Vertically Stacked Nanowire MOSFETS for Sub-10 nm Nodes: Advanced Topography, Device, Variability, and Reliability Simulations
Using an advanced simulation framework we analyze a recent sub-10 nm technology demonstration based on stacked nanowire transistors (NW-FETs). The study encompasses (i) topography simulation which realistically reproduces the fabricated device, (ii) device simulation based on the subband Boltzmann transport equation (iii) a comprehensive set of scattering models for the gate stack, (iv) physical models for time-zero variability and BTI device degradation. We find that (i) the fabrication process introduces parasitic capacitances not present in a comparable FinFET, (ii) the device performance is significantly affected by interface-charge-induced Coulomb scattering resulting in up to 50% reduction in drain current compared to an ideal device, (iii) device time-zero variability is increased due to a lower amount of dopant atoms per device, (iv) the device is more affected by BTI than a comparable FinFET. Using physics-based TCAD for technology path-finding and device optimization, we are able to point out critical improvements required for the stacked NW-FET to surpass current FinFET technology.
Vertically stacked nanowire MOSFETs for sub-10nm nodes: Advanced topography, device, variability, and reliability simulations
Using an advanced simulation framework we analyze a recent sub-10 nm technology demonstration based on stacked nanowire transistors (NW-FETs). The study encompasses (i) topography simulation which realistically reproduces the fabricated device, (ii) device simulation based on the subband Boltzmann transport equation (iii) a comprehensive set of scattering models for the gate stack, (iv) physical models for time-zero variability and BTI device degradation. We find that (i) the fabrication process introduces parasitic capacitances not present in a comparable FinFET, (ii) the device performance is significantly affected by interface-charge-induced Coulomb scattering resulting in up to 50% reduction in drain current compared to an ideal device, (iii) device time-zero variability is increased due to a lower amount of dopant atoms per device, (iv) the device is more affected by BTI than a comparable FinFET. Using physics-based TCAD for technology path-finding and device optimization, we are able to point out critical improvements required for the stacked NW-FET to surpass current FinFET technology.
Phase-Space Solution of the Subband Boltzmann Transport Equation for Nano-Scale TCAD
We present a comprehensive simulation framework for transport modeling in nano-scaled devices based on the solution of the subband Boltzmann transport equation (BTE). The BTE is solved in phase space using a k·p-based electronic structure model and includes all relevant scattering processes. The BTE solver is combined with a conventional drift-diffusion- based simulator using a novel iteration approach. The pairing between BTE, DD, and Poisson results in a flexible toolkit which converges quickly in any mode of operation, allows large- scale parallelization, and to include near-equilibrium transport outside the BTE region, i.e. the contacting regions. The toolkit is commercially available as part of the GTS Nano Device Simulator (NDS). We examine realistic NMOS and PMOS devices, includ- ing transport at the microscopic scale and possible numerical approximations.
Physical Transport Simulation for Path-Finding and Device Optimization
We present a novel simulation approach for transport modeling in nano-scaled devices. It is based on the solution of the Boltzmann transport equation (BTE) in phase space using a k·p-based electronic structure model and includes all relevant scattering processes. The modeling framework is suitable low and high VDD regime and consistently covers all the necessary physics like confinement, velocity overshoot, and quantum resistance to give meaningful predictions using only few material parameters. With a highly efficient numerical implementation, the approach is suitable for both path-finding and device optimization.
Simulation Study on the Feasibility of Si as Material for Ultra-Scaled Nanowire Field-Effect Transistors
We present a simulation framework which allows thorough performance evaluation of ultra-scaled devices. Our simulation approach is based on the full solution of the Boltzmann transport equation (BTE) on subbands as calculated from a k·p-Hamiltonian and including all relevant scattering mechanisms which occur in semiconductors at room temperature. We employ the simulation framework to investigate the performance limits of silicon-based technology for ultra-scaled field-effect transistors in logic applications.
Physical Modeling – a New Paradigm in Device Simulation
We go far beyond classical TCAD in and create a simulation framework that is ready for devices based on contemporary and future technology nodes. We do so by extending the common drift-diffusion-type device simulation framework with additional tools: (i) a k p-based subband structure tool, (ii) a deterministic subband Boltzmann transport solver, and (iii) a TCAD-compatible quantum transport solver, to capture every important aspect of device operation at the nano-scale. An atomistic ab-initio tool suite complements the framework providing material properties that would be hard to obtain otherwise. The capabilities of the approach are demonstrated on two different devices featuring non-planar geometry and alternative channel materials.
Predictive Physical Simulation of III/V Quantum-Well MISFETs for Logic Applications
We present a simulation modeling chain for nano-scaled III/V quantum-well MISFETs. Our methods are based on physical rather than empirical modeling, which allows to obtain predictive simulation results with very few fitting parameters. We use a recent InGaAs-based technology from Intel [1] to validate our simulation results which show excellent agreement with measured capacitance and conductance curves. We further evaluate the properties of a 60 nm long InGaAs quantum-well transistor, finding a sub-threshold slope of 73.5 mV/dec and a DIBL of 103.8 mV/V. A fast numerical computational framework ensures high modeling flexibility; at the same time execution times are kept short making our approach an ideal replacement for empirical device modeling which is still pervasive in TCAD.
New Computational Perspectives on Scattering and Transport in III/V Channel Materials
A physically-grounded modeling, simulation, and parameter-extraction framework that targets design and engineering of ultra-scaled devices and next-generation channel materials. The framework consists of a fast and accurate Schrdinger-Poisson solver/mobility extractor coupled to a device simulator. It brings physical modeling of semiconductor channels to device design and engineering which until now has been the domain of TCAD tools based on purely empirical models. In this work, we specifically explore the framework components required to model devices based on III/V compound semiconductors.
Consistent Low-Field Mobility Modeling for Advanced MOS Devices
In this paper we develop several extensions to semi-classical modeling of low-field mobility, which are necessary to treat planar and non-planar channel geometries on equal footing. We advance the state-of-the-art by generalizing the Prange-Nee model for surface roughness scattering to non-planar geometries, providing a fully numerical treatment of Coulomb scattering, and formulating the Kubo-Greenwood mobility model in a consistent, dimension-independent manner. These extensions allow meaningful comparison of planar and non-planar structures alike, and open the door to evaluating emerging device concepts, such as the FinFET or the junction-less transistor, on physical grounds.
Efficient Modeling of Source/Drain Tunneling in Ultra-Scaled Transistors
In this work, a comprehensive investigation of the effect of source/drain tunneling in ultra-scaled transistors is presented. A novel approach to efficiently and accurately incorporate the quantum-mechanical effects of source/drain (S/D) tunneling in semi-classical device simulators has been developed. The ballistic quantum transport model has been implemented as part of the Vienna-Schrödinger-Poisson simulation and modeling framework. The transport formalism is based on the quantum transmitting boundary method and has been extended to provide recombination and generation rates of carriers due to the direct tunneling current across the source/drain barrier. The model has been used to investigate the effect of direct S/D tunneling on device performance in ultra-scaled double-gate and nanowire transistors. The variations in transfer and output characteristics due to the tunneling effect have been calculated for different gate lengths and channel widths. The influence on the drain induced barrier lowering is shown.
Hierarchical TCAD Device Simulation of FinFETs
A framework for FinFET design studies is presented. Our physics-based modeling approach allows to accurately capture the effects of channel cross-section, orientation and strain as well as contact resistance - for the first time all in one tool. Using this approach as a reference, the predictiveness of empirical TCAD models is extended by re-calibration. Our hierarchical tool chain is embedded in an industry-proven framework equipped with DOE and optimization modules. The capabilities are demonstrated in a simulation study on a recent FinFET technology node.
Layout-Based TCAD Device Model Generation
In this work, a fully automated process emulation is presented. Starting from industrial standard gdsII mask files a user friendly and fast way to create TCAD ready models has been realized. A three step approach is used. The creation of virtual layers to allow for logical operation based on masks is shown. Then the geometrical and dopant profile instantiation is carried out. Third the mesh generation based on and optimized on the information of the first two steps is shown. Industry-relevant sample applications for the implemented work-flow ranging from a radiation hardened latch to a state of the art FinFET SRAM cell are demonstrated.
Expanding TCAD Simulations from Grid to Cloud
In this work, the distribution, execution and performance of TCAD simulations on grid and cloud systems are investigated. A module for distributed computing which can uniformly interface both grid and cloud computing systems has been implemented within GTS Framework. Automated allocation of resources for user jobs on a combined platform has been achieved. Traditional grid-computing systems are compared with cloud-based systems. Strategies for cost-effective allocation of cloud-resources are presented. The performance of a typical TCAD application run on a grid, in the cloud, and a hybrid system combining both are assessed.
Hierarchical TCAD device simulation of FinFETs
A framework for FinFET design studies is presented. Our physics-based modeling approach allows to accurately capture the effects of channel cross-section, orientation and strain as well as contact resistance - for the first time all in one tool. Using this approach as a reference, the predictiveness of empirical TCAD models is extended by re-calibration. Our hierarchical tool chain is embedded in an industry-proven framework equipped with DOE and optimization modules. The capabilities are demonstrated in a simulation study on a recent FinFET technology node.
Bringing Physics to Device Design – a Fast and Predictive Device Simulation Framework
We present a physically grounded modeling, simulation, and parameter-extraction framework that targets design and engineering of ultra-scaled devices and next-generation channel materials. The framework consists of a fast and accurate Schrödinger-Poisson solver/mobility extractor coupled to a device simulator. The framework brings physical modeling of semiconductor channels to device design and engineering which until now has been the domain of TCAD tools based on purely empirical models.
Bringing physics to device design — A fast and predictive device simulation framework
We present a physically grounded modeling, simulation, and parameter-extraction framework that targets design and engineering of ultra-scaled devices and next-generation channel materials. The framework consists of a fast and accurate Schrödinger-Poisson solver/mobility extractor coupled to a device simulator. The framework brings physical modeling of semiconductor channels to device design and engineering which until now has been the domain of TCAD tools based on purely empirical models.
Experimental and Simulation Results of Magnetic Modulation of Gate Oxide Tunneling Current in Nanoscaled MOS Transistors
An experimental-simulation methodology to explore the spatially nonhomogeneous properties of the tunneling current in nanoscaled MOSFET is introduced. The magnetic field $B$ is introduced into the Schrödinger–Poisson system, which allows simulating the effect of the $B$ field on the gate oxide tunneling current and be compared with experimental data. We found out that sweeping the $B$ field from negative to positive values is equivalent to scan or map the tunneling mechanism along the channel from source to drain. The proposed methodology is useful for studying nonhomogeneous space distributed conductive properties, and it was validated with a 28-nm n-type Si MOSFET.
Thermo-Magnetic Effects in Nano-Scaled MOSFET: An Experimental, Modeling, and Simulation Approach
A numerical simulation methodology for incorporating thermo-magnetic effects on the MOSFET gate tunneling current is introduced. The methodology is based on the solution of the Schrödinger-Poisson coupled system, which allows simulating the influence of a static magnetic field and temperature on the wave functions and gate tunneling current of MOSFET devices. In addition to the preliminary results on the simulation methodology, experimental results on the effect of the magnetic field on the subthreshold slope, the off-current, and transconductance, are also introduced. The proposed simulation methodology, in conjunction with experimental data, is useful for device degradation and reliability studies in nano-scaled MOSFET devices. This experimental characterization technique sets also the basis for the development of a magnetic force nanoscopy technique, where the conductive properties, thanks to the Lorentz force, can be two-dimensionally mapped over the nano-scaled MOSFET channel plane.
Investigation of Quantum Transport in Nanoscaled GaN High Electron Mobility Transistors
In this paper, a comprehensive investigation of quantum transport in nanoscaled gallium nitride (GaN) high electron mobility transistors (HEMTs) is presented. A simulation model for quantum transport in nanodevices on unstructured grids in arbitrary dimension and for arbitrary crystal directions has been developed. The model has been implemented as part of the Vienna-Schrödinger-Poisson simulation and modeling framework. The transport formalism is based on the quantum transmitting boundary method. A new approach to reduce its computational effort has been realized. The model has been used to achieve a consistent treatment of quantization and transport effects in deeply scaled asymmetric GaN HEMTs. The self-consistent electron concentration, conduction band edges and ballistic current have been calculated. The effects of strain relaxation at the heterostructure interfaces on the potential andrncarrier concentration have been shown.
On the Validity of Momentum Relaxation Time in Low-Dimensional Carrier Gases
The momentum relaxation time (MRT) is widely used to simplify low-field mobility calculations including anisotropic scattering processes. Although not always fully justified, it has been very practical in simulating transport in bulk and in direction quantity low-dimensional carrier gases alike. We review the assumptions behind the MRT, quantify the error introduced by its usage forrnlow-dimensional carrier gases, and point out its weakness in accounting for inter-subband interaction, occurring specifically at low inversion densities.
Advanced Numerical Methods for Semi-classical Transport Simulation in Ultra-Narrow Channels
In this work we present a semi-classical modeling and simulation approach for ultra-narrow channels that has been implemented as part of the Vienna Schrödinger-Poisson (VSP) simulation framework (Baumgartner, J Comput Electron 12:701–721, 2013; http://www.globaltcad.com/en/products/vsp.html (2014)) over the past few years. Our research has been driven by two goals: maintaining high physical accuracy of the models while producing a computationally efficient and flexible simulation code.
Full-Band Modeling of Mobility in p-type FinFETs
We present a framework for modeling the low-field mobility of ultra-narrow Si channels such as FinFETs based on a full-band description of the electronic structure. Hole mobility is of particular interest since its calculation necessitates a full-band approach. Our approach is entirely based on physical modeling and thus naturally includes effects of gate field, crystal orientation, or strain.
Fast Methods for Full-Band Mobility Calculation
We developed a number of methods targeted at fast full-band mobility calculation of device channels, including: subband structure calculation, determination of couplings in k-space, and evaluation of the transition rates based on our recent modeling efforts of SRS. The entire workflow is implemented within the Vienna Schrödinger-Poisson (VSP) simulation framework. Every step in the process is parallelized with close-to-linear scalability. The resulting performance boost brings full-band mobility modeling one significant step closer tornmainstream TCAD device simulation.
Exploring the Design Space of Non-Planar Channels: Shape, Orientation, and Strain
We conduct a comprehensive simulation study of non-planar n-type channels based on consistent, physical models containing measurable quantities rather than fit-parameters. This contrasts empirical thin-body models used in classical/quantum-corrected TCAD. The method involves the self-consistent solution of the two-dimensional Schrödinger-Poisson system,rncombined with linearized Boltzmann transport in the third dimension. We advance the art of simulation by (i) introducing quantum simulation on unstructured meshes for arbitraryrngeometries, (ii) providing an efficient framework for rapid evaluation of device designs, and (iii) contributing a surface roughness scattering model for arbitrarily shaped surfaces.rnConsistent modeling allows us to make reliable assertions with respect to device performance.
VSP – A Quantum-Electronic Simulation Framework
The Vienna Schrödinger-Poisson (VSP) simulation framework for quantum-electronic engineering applications is presented. It is an extensive software tool that includes models for band structure calculation, self-consistent carrier concentrations including strain, mobility, and transport in transistors and heterostructure devices. The basic physical models are described. Through flexible combination of basic models sophisticated simulation setups for particular problems are feasible. The numerical tools, methods and libraries are presented. A layered software design allows VSP’s existing components such as models and solvers to be combined in a multitude of ways, and new components to be added easily. The design principles of the software are explained. Software abstraction is divided into the data, modeling and algebraic level resulting in a flexible physical modeling tool. The simulator’s capabilities are demonstrated with real-world simulation examples of tri-gate and nanoscale planar transistors, quantum dots, resonant tunneling diodes, and quantum cascade detectors.
Modeling Direct Band-to-Band Tunneling using QTBM
This work focuses on modeling the tunneling mechanism in direct semiconductors. An effective barrier is extracted between the valence and conduction band, by defining the barrier as valence-like near the valence band and conduction band-like near the conduction band. The transition occurs at a point obtained by momentum matching. Computation of transition coefficient is performed using the quantum transmitting boundary method.
Modeling direct band-to-band tunneling using QTBM
This work focuses on modeling the tunneling mechanism in direct semiconductors. An effective barrier is extracted between the valence and conduction band, by defining the barrier as valence-like near the valence band and conduction band-like near the conduction band. The transition occurs at a point obtained by momentum matching. Computation of transition coefficient is performed using the quantum transmitting boundary method.
Surface-Roughness-Scattering in Non-Planar Channels – the Role of Band Anisotropy
We developed a new generic method for evaluating the surface-roughness-induced scattering rate in non-planar semiconductor structures. The method accurately captures band anisotropy and the roughness-induced momentum transfer between the confined states. Strong dependence of SRS-limited electron mobility on crystal orientation was observed with and [110]/(11̄0) being the optimal orientations.
Modeling Surface-Roughness-Induced Scattering in Non-Planar Silicon Nanostructures
We extend the surface roughness scattering formalism for planar structures to non-planar ones. The planar-structure formalism based on theory by Prange and Nee [1] has been widely used for calculating the conductivity of inversion layers and thin films [2]. An extension to cylindrical nanowires has been developed by Jin et al. [3]; their model assumes isotropic band structure in the channel matrial and assigns radial and angular quantum numbers to each state thus facilitating the evaluation of the surface roughness matrix elements. We derive matrix elements for open and closed surfaces of arbitrary shape taking anisotropy of the band structure fullyrninto account. This model is applied to different device cross-sections such as a FinFET or a nanowire.
A versatile finite volume simulator for the analysis of electronic properties of nanostructures
We present a novel semantic approach to modeling and simulation of nanoelectronic devices. The approach is based on a finite volume spatial discretization scheme. The scheme was adapted to accurately treat material anisotropy. It is thus capable of capturing orientation and strain effects both of which are prominent in the nanoscale regime. We also demonstrate the method's simplicity and power with a three-dimensional simulation study of a quantum dot using a six band k · p Hamiltonian for holes as model.
Electron subband structure in strained silicon UTB films from the Hensel–Hasegawa–Nakayama model -- Part 2 efficient self-consistent numerical solution of the k·p schrödinger equation
A self-consistent Schrödinger–Poisson model for the calculation of the electron subband structure of ultra-thin body (UTB) devices for arbitrary substrate orientation is presented. The proposed approach is based on a two-band k · p Hamiltonian and takes the band nonparabolicity and arbitrary strain into account. Despite its small matrix size compared to full-band approaches, an excellent description of the band structure over a wide range of the Brillouin zone is assured. Furthermore, emphasis is put on the efficiency and accuracy of the numerical, two-dimensional k-space integration of the subband distribution functions. For this purpose, the Clenshaw–Curtis method which is based on non-equidistant interpolation nodes is employed. Simulation results of (0 0 1) and (1 1 0) oriented silicon UTB double gate devices demonstrate the suitability of the proposed numerical method. For Si body thicknesses in the nanometer regime, the presence of band structure effects which are not captured by a one-band model are clearly demonstrated.
A Model for Switching Traps in Amorphous Oxides
Negative Bias Temperature Instability (NBTI) is frequently suspected to arise from a delicate interplay between some sort of hole trapping and an interface generation mechanism. In a recently suggested model the E' center along with its second form as an Si - Si dimer are supposed to play a key role. Despite of its successful application to a large amount of experimental data, this model relies on a classical determination of the bandedge energy diagram and the carrier concentrations. The occurrence of subbands in the inversion layer shifts the initial energy level for charge trapping and may thus strongly impact the trapping dynamics. We evaluate the new model against measurement data in order to investigate the impact of quantization effects on the model parameters.
Numerical Quadrature of the Subband Distribution Functions in Strained Silicon UTB Devices
In this work, the k·p method is used to calculate the electronic subband structure. To reduce the computational cost of the carrier concentration calculation and henceforth the required number of numerical solutions of the Schrodinger equation, an efficient 2D k-space integration by means of the Clenshaw-Curtis method is proposed. The suitability of our approach is demonstrated by simulation results of Si UTB double gate nMOS and pMOS devices.
Modeling of high-k-Metal-Gate-stacks using the non-equilibrium Green's function formalism
A high-k-metal-gate stack has been investigated using an open boundary model based on the non-equilibrium Greenpsilas function formalism. The numerical energy integration, which is crucial because of the very narrow resonant states, is pointed out in detail. The model has been benchmarked against the established classical and closed boundary Schrodinger-Poisson model. In contrast to the established models, the solution covers distinct resonant states with a realistic broadening and results in a major difference in the current density spectrum.
A rigorous model for trapping and detrapping in thin gate dielectrics
We rigorously model charge trapping and detrapping in ultrathin dielectrics. In addition to charge exchange with the substrate, the poly-gate interface is taken into account which gives rise to decreased charge trapping compared to conventional models designed for thicker gate dielectrics. Finally, an extension of this model also accounting for the shift of trap levels may possibly explain the large time scales experimentally observed during the recovery after application of an on-state voltage.
Adaptive Energy Integration of Non-Equilibrium Green’s Functions
To obtain the physical quantities of interest within the non-equilibrium Green’s function formalism, numerical integration over energy space is essential. Several adaptive methods have been implemented and tested for their applicability. The number of energy grid points needed and the convergence behaviour of the Schrödinger-Poisson iteration have been evaluated. An adaptive algorithm based on a global error criterion proved to be more efficient than a local adaptive algorithm.
A multi-purpose Schroedinger-Poisson Solver for TCAD applications
We present the Vienna Schrödinger-Poisson Solver (VSP), a multi-purpose quantum mechanical solver for investigations on nano-scaled device structures. VSP includes a quantum mechanical solver for closed as well as open boundary problems on fairly arbitrary one-dimensional cross sections within the effective mass framework. For investigations on novel gate dielectrics VSP holds models for bulk and interface trap charges, and direct and trap assisted tunneling. Hetero-structured semiconductor devices, like resonant tunneling diodes (RTD), can be treated within the closed boundary model for quick estimation of resonant energy levels. The open boundary model allows evaluation of current voltage characteristics.