Cell Designer – a Comprehensive TCAD-Based Framework for DTCO of Standard Logic Cells

Z. Stanojević, G. Strof, F. Schanovsky, K. Steiner, O. Baumgartner, C. Kernstock, and M. Karner
We present the first practical TCAD-based work flow for design-technology co-optimization (DTCO) of standard cells. The flow consists of parametric cell layout templates, layout-based structure generation, mixed-mode transient electrical device simulation, and data collection and analysis. Based on electrical and structural characterizations of the iNt4,iN10, and iN7 nodes, the models presented in this work feature a projection for 5 nm technology nodes based on FinFET, nanowire, and nanosheet. Transient five-stage ring-oscillator simulations show a clear advantage for the FinFET in terms of switching frequency and power consumption.
Publication date: 03 September 2018
Download document (PDF)
Document, read in your PDF viewer; 1 MB
Download PDF

{“@id”:”/api/v1/downloads/3631″,”@type”:”Download”,”id”:3631,”title”:”Cell Designer – a Comprehensive TCAD-Based Framework for DTCO of Standard Logic Cells”,”filename”:”ESSDERC-2018_Cell-Designer-a-Comprehensive-TCAD-Based-Framework-for-DTCO-of-Standard-Logic-Cells”,”abstract”:”We present the first practical TCAD-based work flow for design-technology co-optimization (DTCO) of standard cells. The flow consists of parametric cell layout templates, layout-based structure generation, mixed-mode transient electrical device simulation, and data collection and analysis. Based on electrical and structural characterizations of the iNt4,iN10, and iN7 nodes, the models presented in this work feature a projection for 5 nm technology nodes based on FinFET, nanowire, and nanosheet. Transient five-stage ring-oscillator simulations show a clear advantage for the FinFET in terms of switching frequency and power consumption.”,”level”:null,”doi”:”10.1109/essderc.2018.8486887″,”status”:”published”,”remarks”:”PrimAuthor: Z. Stanojevic”,”files”:[{“@type”:”File”,”id”:30674,”name”:”ESSDERC-2018_Cell-Designer-a-Comprehensive-TCAD-Based-Framework-for-DTCO-of-Standard-Logic-Cells.pdf”,”bytes”:1141846}],”tags”:[{“@id”:”/api/v1/download_tags/10″,”@type”:”DownloadTag”,”id”:10,”name”:”cell designer”},{“@id”:”/api/v1/download_tags/18″,”@type”:”DownloadTag”,”id”:18,”name”:”dtco”},{“@id”:”/api/v1/download_tags/20″,”@type”:”DownloadTag”,”id”:20,”name”:”publication”},{“@id”:”/api/v1/download_tags/32″,”@type”:”DownloadTag”,”id”:32,”name”:”finfet”},{“@id”:”/api/v1/download_tags/46″,”@type”:”DownloadTag”,”id”:46,”name”:”nanowire”},{“@id”:”/api/v1/download_tags/60″,”@type”:”DownloadTag”,”id”:60,”name”:”innovation”},{“@id”:”/api/v1/download_tags/72″,”@type”:”DownloadTag”,”id”:72,”name”:”cell optimization”},{“@id”:”/api/v1/download_tags/98″,”@type”:”DownloadTag”,”id”:98,”name”:”nanosheet”}],”date”:”2018-09-03T00:00:00+02:00″,”authors”:”Z. Stanojević, G. Strof, F. Schanovsky, K. Steiner, O. Baumgartner, C. Kernstock, and M. Karner”}