Modeling of Interface Traps in Nano-scaled Devices – Application Example

{“@id”:”/api/v1/downloads/3198″,”@type”:”Download”,”id”:3198,”title”:”Modeling of Interface Traps in Nano-scaled Devices – Application Example”,”filename”:”NDS_Interface_Traps”,”abstract”:”Demonstrates the usage of the GTS Nano Device Simulator (NDS) to model a 3D nanowire FET with interface charges. “,”level”:3,”doi”:null,”status”:”published”,”remarks”:null,”files”:[{“@type”:”File”,”id”:29937,”name”:”NDS_Interface_Traps.pdf”,”bytes”:1308930},{“@type”:”File”,”id”:29938,”name”:”NDS_Interface_Traps.zip”,”bytes”:4080253},{“@type”:”File”,”id”:29939,”name”:”NDS_Interface_Traps.png”,”bytes”:14442}],”tags”:[{“@id”:”/api/v1/download_tags/16″,”@type”:”DownloadTag”,”id”:16,”name”:”doe”},{“@id”:”/api/v1/download_tags/23″,”@type”:”DownloadTag”,”id”:23,”name”:”example”},{“@id”:”/api/v1/download_tags/46″,”@type”:”DownloadTag”,”id”:46,”name”:”nanowire”},{“@id”:”/api/v1/download_tags/58″,”@type”:”DownloadTag”,”id”:58,”name”:”nds”},{“@id”:”/api/v1/download_tags/70″,”@type”:”DownloadTag”,”id”:70,”name”:”si pathfinding”},{“@id”:”/api/v1/download_tags/109″,”@type”:”DownloadTag”,”id”:109,”name”:”TutExaCat-Area: Technology Path-Finding”},{“@id”:”/api/v1/download_tags/110″,”@type”:”DownloadTag”,”id”:110,”name”:”TutExaCat-Appl.: Advanced CMOS Logic”},{“@id”:”/api/v1/download_tags/111″,”@type”:”DownloadTag”,”id”:111,”name”:”TutExaCat-Tool: GTS Nano Device Simulator”},{“@id”:”/api/v1/download_tags/148″,”@type”:”DownloadTag”,”id”:148,”name”:”TutExaCat-Appl.: Reliability & Variability”},{“@id”:”/api/v1/download_tags/187″,”@type”:”DownloadTag”,”id”:187,”name”:”release-gts-2026-03″}],”date”:”2026-06-18T00:00:00+02:00″,”authors”:null}