Preview

GTS Nano Device Simulator Gate-All-Around FinFET - Application Example

Modeling nMOS gate-all-around (GAA) FinFET transistors using GTS Nano Device Simulator (NDS). The impact of gate length, channel orientation and mechanical stress is investigated.
Project Name: NDS_GAA_FinFET
PDF revision of 27 August 2025
Download document only (PDF)
Document, read in your PDF viewer; 2 MB
Download PDF
Download project (data + PDF)
Simulation files for GTS Framework; 61 MB
Download PDF

{“@id”:”/api/v1/downloads/2833″,”@type”:”Download”,”id”:2833,”title”:”GTS Nano Device Simulator Gate-All-Around FinFET – Application Example”,”filename”:”NDS_GAA_FinFET”,”abstract”:”Modeling nMOS gate-all-around (GAA) FinFET transistors using GTS Nano Device Simulator (NDS). The impact of gate length, channel orientation and mechanical stress is investigated. “,”level”:2,”doi”:null,”status”:”published”,”remarks”:null,”files”:[{“@type”:”File”,”id”:24096,”name”:”NDS_GAA_FinFET.png”,”bytes”:24637},{“@type”:”File”,”id”:24097,”name”:”NDS_GAA_FinFET.pdf”,”bytes”:1951800},{“@type”:”File”,”id”:24098,”name”:”NDS_GAA_FinFET.zip”,”bytes”:63514450}],”tags”:[{“@id”:”/api/v1/download_tags/16″,”@type”:”DownloadTag”,”id”:16,”name”:”doe”},{“@id”:”/api/v1/download_tags/23″,”@type”:”DownloadTag”,”id”:23,”name”:”example”},{“@id”:”/api/v1/download_tags/58″,”@type”:”DownloadTag”,”id”:58,”name”:”nds”},{“@id”:”/api/v1/download_tags/70″,”@type”:”DownloadTag”,”id”:70,”name”:”si pathfinding”},{“@id”:”/api/v1/download_tags/96″,”@type”:”DownloadTag”,”id”:96,”name”:”gaa”},{“@id”:”/api/v1/download_tags/109″,”@type”:”DownloadTag”,”id”:109,”name”:”TutExaCat-Area: Technology Path-Finding”},{“@id”:”/api/v1/download_tags/110″,”@type”:”DownloadTag”,”id”:110,”name”:”TutExaCat-Appl.: Advanced CMOS Logic”},{“@id”:”/api/v1/download_tags/111″,”@type”:”DownloadTag”,”id”:111,”name”:”TutExaCat-Tool: GTS Nano Device Simulator”},{“@id”:”/api/v1/download_tags/180″,”@type”:”DownloadTag”,”id”:180,”name”:”release-gts-2025-03″}],”date”:”2025-08-27T00:00:00+02:00″,”authors”:null}