Optimize Designs Across Technologies

For the last few decades, the semiconductor industry was increasingly driven by the foundry and the fabless model. Foundries have focused on the expensive process of improving and creating new transistor technology at reduced cost per functionality. Fabless companies build their business on IC design and product marketing while relying on the foundries for manufacturing. The main technical communication point in this mutually beneficial relationship is the Process Design Kit (PDK), which contains all the information for the fabless Customer Owned Tooling (COT) flow to complete a design for a given foundry technology. This clean separation is increasingly getting under technological and financial pressure. New levels of collaboration between Foundry and Fabless are essential to achieve the time-to-market while meeting the unprecedented reliability requirements for today’s applications complementing the usual performance/cost/yield considerations.

Illustration: information flow between foundry and customer
Information flow: Fab/foundry – Designer/customer

DTCO: The Mediator Process

There is great need for effective design-technology co-optimization (DTCO) methods in chip design to tackle new market opportunities and revolutions of the semiconductor industry including mobile communication (5G), autonomous vehicles and green mobility and mobility services, smart medicine, artificial intelligence and machine learning as well as the Internet of Things (IoT). The challenges faced at the most advanced technology nodes can be overcome with the help of DTCO. It is not a specific solution or even a rigorous engineering approach; it is a mediation process between circuit designers and process engineers that aims to ensure a competitive technology architecture definition while avoiding schedule or yield risks caused by unrealistically aggressive process assumptions. The abstractions and tools common to both engineering disciplines should be a part of the process.

GTS provides an automated TCAD-based DTCO solution that is suitable for both – the design houses’ EDA tool flow as well as the foundries’ PDK-preview generation – resolving the communications barrier between foundries and fabless.

Technology to Circuit – and Back

Ahead of Market, Ahead in Technologies

Whether you want to assess the power-performance-area (PPA) of a ring oscillator based on FinFET, nanosheet or nanowire technology or optimize the static noise margin of your SRAM design: A TCAD-based DTCO approach will provide valuable insights ahead of market. So far, compact transistor models along with extracted R/C-networks have been the backbone of DTCO efforts in the context of circuits, functions, blocks, and even entire SoCs. TCAD simulations haven’t played a major role in DTCO yet, apart from steady-state single-transistor simulations for calibrating compact models. Full transient TCAD device simulations of cells are still uncommon, especially in design.

With a handful of tools – carry out a PPA analysis for a set of design and technology choices.

The Best of Both Worlds

Using GTS’ DTCO solution, you will be able to enjoy the best of both worlds. You can employ our automated flow to generate TCAD-based Spice models combined with an accurate netlist of the parasitcs provided by our field-solver for fast PPA evaluation. You can investigate time-zero variability as well as reliability in a consistent manner. Most importantly, you can verify your results in greatest detail by running a full 3D TCAD analysis of your design and technology choices.

GTS presents the first practical TCAD-based workflow for design-technology co-optimization (DTCO) of standard cells as part of the GTS Cell Designer product suite. Cell Designer provides parametrized cell layout templates, layout-based structure generation, mixed-mode transient electrical device simulation, automated Spice model extraction, field-solver based parasitics extraction, automated netlist generation, and data collection and analysis.

illustration showing workflow of GTS cell designer



Design technology co-optimization (DTCO): From the layout and technology description, a complete standard cell is created and simulated in a TCAD tool. Variability is included on cell and device level. Physical transport parameters are extracted from predictive device simulations (NDS). The TCAD calculations deliver all relevant metrics (Power/Performance/Variability/Reliability) for the standard cell and intrinsically consider all coupling effects (e.g. parasitics). Enable your design team to assess early technology information to optimize your layout.

Take a closer look at the new way to optimize your cells and circuits. Find out about the tools, that provide accurate netlists and Spice models in our integrated and automated DTCO flow.

Cell/Circuit Optimization

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Layout to Circuit

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