2. December 2022
In his 2022 IEDM paper, GTS scientist Gerhard Rzepa uses a performance and variability-aware DTCO flow to benchmark nanosheet SRAM cells against fin technologies at 3nm node, targeted at 45 nm CPP and 21 nm MP.
Join Gerhard’s talk at IEDM 2022!
Horizontal Gate-All-Around Nanosheet Devices
For the 3nm technology node, horizontal gate-all- around nanosheet devices offer a non-disruptive process transition from fin technologies with the advantage of full 3D design flexibility and better short-channel control. For SRAM cell design, this enables non-digital n/pFET balancing.
Performance & Variability, Benefits gaind by New Design Freedom
The impact of gate length, fin height, number of nanosheets, effective n/pFET widths, channel doping, and vertical nanosheet pitch is studied. Despite the lower parasitic capacitances of fins, the design freedoms of nanosheets enable superior SRAM operation in terms of both Vmin and read delay even at smaller cell areas.
Hear the Talk at IEDM 2022!
Session 15: MS – Advanced TCAD Methodology
Tuesday, December 6, 9:00 a.m. Continental Ballroom 7-9
15.1 Performance and Variability-Aware SRAM Design for Gate-All-Around Nanosheets and Benchmark with FinFETs at 3nm Technology Node
IEDM website, Technical program
Update: The paper is available here via MyGTS login.