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DTCO FinFET N7 Spice RO with Var. and Rel. - Application Example

In this example, PEX of inverter cells in FinFET technology are conducted to obtain their full SPICE netlists. Together with the corresponding transistor model cards, these netlists are used for accurate and fast simulation of RO KPIs including variability (RDD, MGG, and geometrical) and reliability (oxide degradation).
Project Name: DTCO_FinFET_N7_Spice_RO_RelVar
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{“@id”:”/api/v1/downloads/2005″,”@type”:”Download”,”id”:2005,”title”:”DTCO FinFET N7 Spice RO with Var. and Rel. – Application Example”,”filename”:”DTCO_FinFET_N7_Spice_RO_RelVar”,”abstract”:” In this example, PEX of inverter cells in FinFET technology are conducted to obtain their full SPICE netlists. Together with the corresponding transistor model cards, these netlists are used for accurate and fast simulation of RO KPIs including variability (RDD, MGG, and geometrical) and reliability (oxide degradation). “,”level”:3,”doi”:null,”status”:”published”,”remarks”:null,”files”:[{“@type”:”File”,”id”:17584,”name”:”DTCO_FinFET_N7_Spice_RO_RelVar.png”,”bytes”:13135},{“@type”:”File”,”id”:17585,”name”:”DTCO_FinFET_N7_Spice_RO_RelVar.zip”,”bytes”:50095751},{“@type”:”File”,”id”:17586,”name”:”DTCO_FinFET_N7_Spice_RO_RelVar.pdf”,”bytes”:549521}],”tags”:[{“@id”:”/api/v1/download_tags/16″,”@type”:”DownloadTag”,”id”:16,”name”:”doe”},{“@id”:”/api/v1/download_tags/18″,”@type”:”DownloadTag”,”id”:18,”name”:”dtco”},{“@id”:”/api/v1/download_tags/23″,”@type”:”DownloadTag”,”id”:23,”name”:”example”},{“@id”:”/api/v1/download_tags/31″,”@type”:”DownloadTag”,”id”:31,”name”:”structure”},{“@id”:”/api/v1/download_tags/32″,”@type”:”DownloadTag”,”id”:32,”name”:”finfet”},{“@id”:”/api/v1/download_tags/73″,”@type”:”DownloadTag”,”id”:73,”name”:”layout to circuit”},{“@id”:”/api/v1/download_tags/74″,”@type”:”DownloadTag”,”id”:74,”name”:”parasitics extraction”},{“@id”:”/api/v1/download_tags/114″,”@type”:”DownloadTag”,”id”:114,”name”:”TutExaCat-Area: DTCO / Technology to Design”},{“@id”:”/api/v1/download_tags/115″,”@type”:”DownloadTag”,”id”:115,”name”:”TutExaCat-Appl.: DTCO, Cell/Circuit Optimization”},{“@id”:”/api/v1/download_tags/116″,”@type”:”DownloadTag”,”id”:116,”name”:”TutExaCat-Appl.: Layout to Circuit, Parasitics Extraction”},{“@id”:”/api/v1/download_tags/118″,”@type”:”DownloadTag”,”id”:118,”name”:”TutExaCat-Tool: GTS Cell Designer”},{“@id”:”/api/v1/download_tags/148″,”@type”:”DownloadTag”,”id”:148,”name”:”TutExaCat-Appl.: Reliability & Variability”},{“@id”:”/api/v1/download_tags/165″,”@type”:”DownloadTag”,”id”:165,”name”:”release-gts-2023-03″}],”date”:”2023-11-20T00:00:00+01:00″,”authors”:null}