Performance and Variability-Aware SRAM Design for Gate-All-Around Nanosheets and Benchmark with FinFETs at 3nm Technology Node

Gerhard Rzepa, Krishna K. Bhuwalka, Oskar Baumgartner, Daniele Leonelli, Hui-Wen Karner, Franz Schanovsky, Christian Kernstock, Zlatan Stanojević, Hao Wu, Francis Benistant, Changze Liu, and Markus Karner
For the 3nm technology node, horizontal gate-all- around nanosheet devices offer a non-disruptive process tran- sition from fin technologies with the advantage of full 3D design flexibility and better short-channel control. For SRAM cell design, this enables non-digital n/pFET balancing. In this paper, a performance and variability-aware DTCO flow is used to benchmark nanosheet SRAM cells against fin technologies at 3nm node, targeted at 45 nm CPP and 21 nm MP. The impact of gate length, fin height, number of nanosheets, effective n/pFET widths, channel doping, and vertical nanosheet pitch is studied. Despite the lower parasitic capacitances of fins, the design freedoms of nanosheets enable superior SRAM operation in terms of both Vmin and read delay even at smaller cell areas.
Publication date: 06 December 2022
Download document (PDF)
Document, read in your PDF viewer; 2 MB
Download PDF

{“@id”:”/api/v1/downloads/1796″,”@type”:”Download”,”id”:1796,”title”:”Performance and Variability-Aware SRAM Design for Gate-All-Around Nanosheets and Benchmark with FinFETs at 3nm Technology Node”,”filename”:”IEDM-2022_Performance-and-Variability-Aware-SRAM-Design”,”abstract”:”For the 3nm technology node, horizontal gate-all- around nanosheet devices offer a non-disruptive process tran- sition from fin technologies with the advantage of full 3D design flexibility and better short-channel control. For SRAM cell design, this enables non-digital n/pFET balancing. In this paper, a performance and variability-aware DTCO flow is used to benchmark nanosheet SRAM cells against fin technologies at 3nm node, targeted at 45 nm CPP and 21 nm MP. The impact of gate length, fin height, number of nanosheets, effective n/pFET widths, channel doping, and vertical nanosheet pitch is studied. Despite the lower parasitic capacitances of fins, the design freedoms of nanosheets enable superior SRAM operation in terms of both Vmin and read delay even at smaller cell areas.”,”level”:null,”doi”:null,”status”:”published”,”remarks”:”Gerhard 2022 IEDM”,”files”:[{“@type”:”File”,”id”:13661,”name”:”IEDM-2022_Performance-and-Variability-Aware-SRAM-Design.pdf”,”bytes”:2134923}],”tags”:[{“@id”:”/api/v1/download_tags/10″,”@type”:”DownloadTag”,”id”:10,”name”:”cell designer”},{“@id”:”/api/v1/download_tags/18″,”@type”:”DownloadTag”,”id”:18,”name”:”dtco”},{“@id”:”/api/v1/download_tags/20″,”@type”:”DownloadTag”,”id”:20,”name”:”publication”},{“@id”:”/api/v1/download_tags/32″,”@type”:”DownloadTag”,”id”:32,”name”:”finfet”},{“@id”:”/api/v1/download_tags/59″,”@type”:”DownloadTag”,”id”:59,”name”:”pathfinding”},{“@id”:”/api/v1/download_tags/70″,”@type”:”DownloadTag”,”id”:70,”name”:”si pathfinding”},{“@id”:”/api/v1/download_tags/72″,”@type”:”DownloadTag”,”id”:72,”name”:”cell optimization”},{“@id”:”/api/v1/download_tags/73″,”@type”:”DownloadTag”,”id”:73,”name”:”layout to circuit”},{“@id”:”/api/v1/download_tags/74″,”@type”:”DownloadTag”,”id”:74,”name”:”parasitics extraction”},{“@id”:”/api/v1/download_tags/87″,”@type”:”DownloadTag”,”id”:87,”name”:”variability”},{“@id”:”/api/v1/download_tags/96″,”@type”:”DownloadTag”,”id”:96,”name”:”gaa”},{“@id”:”/api/v1/download_tags/98″,”@type”:”DownloadTag”,”id”:98,”name”:”nanosheet”},{“@id”:”/api/v1/download_tags/101″,”@type”:”DownloadTag”,”id”:101,”name”:”sram”}],”date”:”2022-12-06T09:00:00+01:00″,”authors”:”Gerhard Rzepa, Krishna K. Bhuwalka, Oskar Baumgartner, Daniele Leonelli, Hui-Wen Karner, Franz Schanovsky, Christian Kernstock, Zlatan Stanojevi\u0107, Hao Wu, Francis Benistant, Changze Liu, and Markus Karner”}