Understanding the ISPP Slope in Charge Trap Flash Memory and its Impact on 3-D NAND Scaling

D. Verreck, A. Arreghini, F. Schanovsky, G. Rzepa, Z. Stanojević, F. Mitterbauer, C. Kernstock, O. Baumgartner, M. Karner, G. Van den bosch, M. Rosmeulen
We present a physical modeling approach that explains the non-ideal ISPP slope in charge trap layer (CTL) flash memory and its impact on 3-D NAND vertical pitch scaling. First, we derive an expression for the VT change rate and use its field dependence to reproduce experimental vertical NAND ISPP slopes. Next, we implement a 2.5-D TCAD model based on these insights and show significant program voltage increase (>5V) in realistic 3-D NAND flash devices with scaling vertical pitch (down to 10nm). Finally, we evaluate high-k CTL and airgaps as mitigation measures at scaled pitch.
Publication date: 16 December 2021
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{“@id”:”/api/v1/downloads/1898″,”@type”:”Download”,”id”:1898,”title”:”Understanding the ISPP Slope in Charge Trap Flash Memory and its Impact on 3-D NAND Scaling”,”filename”:”IEDM-2021_Understanding_the_ISPP_Slope_in_Charge_Trap_Flash_Memory_and_its_Impact”,”abstract”:”We present a physical modeling approach that explains the non-ideal ISPP slope in charge trap layer (CTL) flash memory and its impact on 3-D NAND vertical pitch scaling. First, we derive an expression for the VT change rate and use its field dependence to reproduce experimental vertical NAND ISPP slopes. Next, we implement a 2.5-D TCAD model based on these insights and show significant program voltage increase (>5V) in realistic 3-D NAND flash devices with scaling vertical pitch (down to 10nm). Finally, we evaluate high-k CTL and airgaps as mitigation measures at scaled pitch.”,”level”:null,”doi”:”10.1109/IEDM19574.2021.9720506″,”status”:”published”,”remarks”:”According to G. Rzepa, who has asked Devin: Devin sent this preprint for publication to GR on 2023/03/09″,”files”:[{“@type”:”File”,”id”:13967,”name”:”IEDM-2021_Understanding_the_ISPP_Slope_in_Charge_Trap_Flash_Memory_and_its_Impact.pdf”,”bytes”:619002}],”tags”:[{“@id”:”/api/v1/download_tags/11″,”@type”:”DownloadTag”,”id”:11,”name”:”minimos”},{“@id”:”/api/v1/download_tags/20″,”@type”:”DownloadTag”,”id”:20,”name”:”publication”},{“@id”:”/api/v1/download_tags/31″,”@type”:”DownloadTag”,”id”:31,”name”:”structure”},{“@id”:”/api/v1/download_tags/51″,”@type”:”DownloadTag”,”id”:51,”name”:”vnand”},{“@id”:”/api/v1/download_tags/76″,”@type”:”DownloadTag”,”id”:76,”name”:”memory simulation”},{“@id”:”/api/v1/download_tags/86″,”@type”:”DownloadTag”,”id”:86,”name”:”reliability”},{“@id”:”/api/v1/download_tags/103″,”@type”:”DownloadTag”,”id”:103,”name”:”physical modeling”}],”date”:”2021-12-16T00:00:00+01:00″,”authors”:”D. Verreck, A. Arreghini, F. Schanovsky, G. Rzepa, Z. Stanojevi\u0107, F. Mitterbauer, C. Kernstock, O. Baumgartner, M. Karner, G. Van den bosch, M. Rosmeulen”}