Understanding the ISPP Slope in Charge Trap Flash Memory and its Impact on 3-D NAND Scaling

D. Verreck, A. Arreghini, F. Schanovsky, G. Rzepa, Z. Stanojević, F. Mitterbauer, C. Kernstock, O. Baumgartner, M. Karner, G. Van den Bosch, and M. Rosmeulen
We present a physical modeling approach that explains the non-ideal ISPP slope in charge trap layer (CTL) flash memory and its impact on 3-D NAND vertical pitch scaling. First, we derive an expression for the VT change rate and use its field dependence to reproduce experimental vertical NAND ISPP slopes. Next, we implement a 2.5-D TCAD model based on these insights and show significant program voltage increase (>5V) in realistic 3-D NAND flash devices with scaling vertical pitch (down to 10nm). Finally, we evaluate high-k CTL and airgaps as mitigation measures at scaled pitch.
DOI: 10.1109/iedm19574.2021.9720506
Publication date: 11 December 2021
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