DRAM Cell Transistors
DRAM cells are today’s most important volatile memory technology and are found in every computing device. As the information in DRAM cells is stored capacitively, the cell transistors have to fulfill very tight specifications with respect to off-state leakage.
Design and Optimization of DRAM Cell Transistors
GTS Framework provides a fast and efficient solution for the design and optimization of high-speed and low-power DRAM cell transistors. Easy-to-use structure templates are available for the generation of state-of-the-art cell transistor geometries, e.g. the saddle-fin structure.
GTS Minimos-NT offers simulation models for storage node leakage (SN LKG) as a function of doping, temperature, gate work-function, and bias conditions. Reverse junction leakage is modeled by Shockley-Read-Hall (SRH) bulk traps including the field enhancement effect. By using discrete traps, statistical properties of the junction leakage can be described.
Gate-induced drain leakage (GIDL) is calculated accurately using quantum mechanical tunneling models on leakage paths through the oxide. The tunneling paths are placed fully automatically to capture the DRAM’s complex geometry. The predictions can be used to meet off-leakage control in order to reduce the refresh time.
GTS tools allow the calculation of operation current (Iop). The effect of discrete random traps and dopants can be simulated statistically, which in few cases may result in significant on-current reduction. Quantum confinement can be incorporated by standard density gradient (DG) quantum correction or by a full solution of the Schrödinger equation. Short channel effects (SCE) are included by proper calibration against SB-BTE simulation results from GTS Nano Device Simulator (NDS). The simulations are used to target drain-induced barrier lowering (DIBL), sub-threshold swing and trans-conductance for superior current-drive ability.
GTS Minimos NT – simulate semiconductor devices and circuits: Run steady-state, transient, and small-signal analysis of arbitrary 2D and 3D device geometries. Combine multiple devices in a circuit with compact models. Run thermal analysys of devices and circuits.
GTS Nano Device Simulator – the first complete solution for effective physical simulation of nano-devices across technology nodes. Get profound predictive data for new materials and device architectures.
GTS Framework – the solid base of all GTS products and your working environment. Includes device editing, file management, distributed job execution, visualization, post-processing, a Python interface, etc.