10. September 2018
GTS presenting first practical TCAD-based work flow for design-technology co-optimization (DTCO) of standard cells.
TCAD-based DTCO Flow for Standard Logic Cells
TCAD-based DTCO faces several issues regarding structure generation, model validity and simulation time. Full transient TCAD device simulation of cells are still uncommon, especially in design. Adressing the above issues, the tool flow demonstrated by GTS provides
- realistic cell geometry generation without detailed process information
- improved turn-around times
- a sound physical basis for transport model calibration with Nano Device Simulator (NDS).
Projections for Future Technology Nodes
The work flow shown by GTS consists of parametric cell layout templates, layout-based structure generation, mixed-mode transient electrical device simulation, and data collection and analysis. Based on electrical and structural characterizations of the IMEC 14nm technology node, the models presented in this work feature a projection for 5nm technology nodes based on FinFET, nanowire, and nanosheet. Transient five-stage ring-oscillator simulations show a clear advantage for the FinFET in terms of switching frequency and power consumption.
In the paper, the capabilities of Cell Designer are demonstrated in a power-performance analysis of ring-oscillators based on FinFET, NWFET, and NSFET technologies.
The image at the right shows an electrostatic potential snapshot in the FinFET-based ring-oscillator; potential is solved in both the FEOL (transistors, contacts) and the BEOL (interconnects) simultaneously.
GTS Cell Designer (CD) is integrated within GTS Framework.