1. December 2021

Charge Trap Flash Memory, Technologies for Artificial Intelligence

A lot to talk about: Our cooperations with IMEC on VNAND, and the University of Bordeaux on technologies for artificial intelligence (AI). Learn why physics-based device simulation in fact is a prerequisite for getting dependable and accurate predictions for upcoming technology nodes.

New Insights on ISPP, Valuable for 3D NAND

Hear Devin Verreck’s (imec) talk “Understanding the ISPP Slope in Charge Trap Flash Memory and its Impact on 3D NAND Scaling“, co-authored by GTS scientists. Devin presents a compact physical description explaining the non-ideal ISPP slope in charge trap flash memories. This mathematical model is the most recent outcome of the enormously productive cooperation of IMEC and GTS during several years. The model is verified against TCAD calculations and a realistic 2.5-D TCAD model is used to investigate process variations such as vertical pitch scaling, high-k CTL and airgaps for program voltage mitigation.

Session 8: Modeling and Simulation – Memory Technology
Monday December 13, 2:50 PM, Session 8-4, Continental Ballrooms 7-9

Laying Grounds for Embedded Artificial Intelligence: FVLLMONTI

Prof. Cristell Maneux of the University of Bordeaux presents our latest contribution to the Horizon 2020 project FVLLMONTI in her invited talk “Modelling of vertical and ferroelectric junctionless technology for efficient 3D neural network compute cube dedicated to embedded artificial intelligence“. Cristell shows the set of simulation means used to develop the N2C2 concept (neural network compute cube) based on the vertical transistor technology platform. Compact modeling, TCAD and EM simulation are leveraged through Design-Technology Co-Optimization (DTCO) to achieve 3D circuit architectures. System-Technology Co-Optimization implications on 3D NN system architecture are explored.

Session 15: Modeling and Simulation – Ferroelectric Microwave, Millimeter Wave and Analogerials, Devices and Applications
Tuesday, December 14, 11:35 AM, Session 15-6, Continental Ballrooms 7-9

Extracted resistance network of an inverter in vertical junctionless NW technology; the doping is shown in the wires
DTCO Flow as presented by G. Rzepa in his 2021 IEDM paper
Examples for 3nm layouts for FIN (left) in 122 configuration and for NSH (right) with 5 nm pFET and 11 nm nFET widths (5-11-11)
The read delay degrades (left) while Vmin improves with increasing cell area (right) for both FIN and NSH
NWFET: Set of trajectories extracted at different energies from energy-scape in k-space
Phase-space plot of the Hamiltonian of the lowest subband in a NWFET; the vertical grid lines correspond to the k-grid, while the horizontal grid lines correspond to cuts (and their refinements); colors indicate the total particle energy (potential + kinetic) of each state, which is obtained by the numerical solution of the k · p Schrödinger equation for each cut position x and wavevector kx; the purple lines highlight two possible ballistic trajectories at a given energy E0.

Path-Finding, DTCO, A Lot More

IRPS Paper: Reliability and Variability-Aware DTCO Flow – N3 FinFET and Nanosheet

In his recent IRPS presentation, Gerhard demonstrated a reliability and variability-aware DTCO flow with logic cells. His simulation flow for DTCO combines the accuracy of TCAD with the performance of SPICE – utilizing parasitic extractions (PEX), the impedance field method for variations, and the compact-physics simulator Comphy for reliability.

As expected, he found good agreement with experimental RO performance of iN14. Based on this, Gerhard made projections to N3 FinFET and nanosheet technologies.

TED Paper: NDS – A Practical Subband-BTE Solver for Path-Finding and DTCO

In his recent TED paper, GTS CTO Zlatan Stanojević presents an in-depth discussion on the subband Boltzmann Transport (SBTE) methodology. He shows a wide range of applications that SBTE is perfect for, including state-of-the art non-planar and well-established planar technologies. Zlatan demonstrates how SBTE can be employed both as a path-finding tool and as a fundamental component in a DTCO flow.

IEEE IEDM 2021

67th Annual IEEE International Electron Devices Meeting – in-person conference December 11-15 at the Hilton San Francisco Union Squarevisit IEDM Web site

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