6. May 2021

A new SRAM architecture based on vertical surrounding gate transistor (SGT) technology was designed for the 1.5nm node by Unisantis in cooperation with GTS using GTS’ DTCO flow.

The paper “1.5-nm Node Surrounding Gate Transistor (SGT)-SRAM Cell with Staggered Pillar and Self-Aligned Process for Gate, Bottom Contact, and Pillar“ will be presented by Yisuo Li at virtual IMW International Memory Workshop on May 21st, 10:20 am (CEST).

The novel architecture doubles the SRAM density achievable by conventional technologies.

SGT device performance predictions by GTS Nano Device Simulator (NDS) were combined with the DTCO, PEX, and circuit simulation capabilities of GTS CellDesigner (CD) to achieve accurate, physics-based, electrical simulations of the SGT-based SRAM cells.

For more on our simulation tools, go to GTS Nano Device Simulator (NDS) or CellDesigner (CD).

1.5nm SRAM cell
1.5nm SRAM cell
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