We present a simulation framework which allows thorough performance evaluation of ultra-scaled devices. Our simulation approach is based on the full solution of the Boltzmann transport equation (BTE) on subbands as calculated from a k·p-Hamiltonian and including all relevant scattering mechanisms which occur in semiconductors at room temperature. We employ the simulation framework to investigate the performance limits of silicon-based technology for ultra-scaled field-effect transistors in logic applications.
Publication date: 27 January 2016
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