DTCO - Extraction of FEOL / MOL Gate C components – Application Example

{“@id”:”/api/v1/downloads/3179″,”@type”:”Download”,”id”:3179,”title”:”DTCO – Extraction of FEOL / MOL Gate C components – Application Example”,”filename”:”FEOL_GateCapacitanceExtraction_FinFET”,”abstract”:” In this example front- and mid-of-line (FEOL/MOL) gate capacitance components are extracted with an automated TCAD flow. There are two extraction methods presented, of which one will employ gate-length modulation to validate the accuracy of the more efficient approach. “,”level”:3,”doi”:null,”status”:”published”,”remarks”:null,”files”:[{“@type”:”File”,”id”:29887,”name”:”FEOL_GateCapacitanceExtraction_FinFET.png”,”bytes”:13042},{“@type”:”File”,”id”:29888,”name”:”FEOL_GateCapacitanceExtraction_FinFET.zip”,”bytes”:35526389},{“@type”:”File”,”id”:29889,”name”:”FEOL_GateCapacitanceExtraction_FinFET.pdf”,”bytes”:955676}],”tags”:[{“@id”:”/api/v1/download_tags/18″,”@type”:”DownloadTag”,”id”:18,”name”:”dtco”},{“@id”:”/api/v1/download_tags/23″,”@type”:”DownloadTag”,”id”:23,”name”:”example”},{“@id”:”/api/v1/download_tags/114″,”@type”:”DownloadTag”,”id”:114,”name”:”TutExaCat-Area: DTCO / Technology to Design”},{“@id”:”/api/v1/download_tags/115″,”@type”:”DownloadTag”,”id”:115,”name”:”TutExaCat-Appl.: DTCO, Cell/Circuit Optimization”},{“@id”:”/api/v1/download_tags/116″,”@type”:”DownloadTag”,”id”:116,”name”:”TutExaCat-Appl.: Layout to Circuit, Parasitics Extraction”},{“@id”:”/api/v1/download_tags/118″,”@type”:”DownloadTag”,”id”:118,”name”:”TutExaCat-Tool: GTS Cell Designer”},{“@id”:”/api/v1/download_tags/187″,”@type”:”DownloadTag”,”id”:187,”name”:”release-gts-2026-03″}],”date”:”2026-06-18T00:00:00+02:00″,”authors”:null}