Design Decoupling of Inner- and Outer-Gate Lengths in Nanosheet FETs for Ultimate Scaling

{“@id”:”/api/v1/downloads/3701″,”@type”:”Download”,”id”:3701,”title”:”Design Decoupling of Inner- and Outer-Gate Lengths in Nanosheet FETs for Ultimate Scaling”,”filename”:”JEDS-2025_Design-Decoupling-of-Inner-and-Outer-Gate-Lengths-in-Nanosheet-FETs-for-Ultimate-Scaling”,”abstract”:”Using a full design-technology-co-optimization (DTCO) methodology, we show the advantages of design decoupling of inner – and outer-gates in gate-all-around nanosheet FETs. Trade-off between short-channel effects (SSAT), external resistance (REXT), effective capacitance (CEFF including parasitic capacitance CPARA) favors for a more aggressive outer-LG scaling (reduces CPARA and/or relaxes contact length, LCNT) keeping inner-LG relaxed (controls REFF, SSAT). Up to 10% speed-at-iso-leakage and speed-at-iso-power, and 15% power-at-iso-speed gains are possible with this unique design available in GAA-NS based devices, allowing for multi-node GAA extension without scaling more fundamental geometry parameters like thickness of NS.”,”level”:null,”doi”:”10.1109/jeds.2024.3492722″,”status”:”published”,”remarks”:”CoAuthor: O. Baumgartner”,”files”:[{“@type”:”File”,”id”:30720,”name”:”JEDS-2025_Design-Decoupling-of-Inner-and-Outer-Gate-Lengths-in-Nanosheet-FETs-for-Ultimate-Scaling.nofile”,”bytes”:0}],”tags”:[{“@id”:”/api/v1/download_tags/18″,”@type”:”DownloadTag”,”id”:18,”name”:”dtco”},{“@id”:”/api/v1/download_tags/20″,”@type”:”DownloadTag”,”id”:20,”name”:”publication”},{“@id”:”/api/v1/download_tags/96″,”@type”:”DownloadTag”,”id”:96,”name”:”gaa”},{“@id”:”/api/v1/download_tags/98″,”@type”:”DownloadTag”,”id”:98,”name”:”nanosheet”},{“@id”:”/api/v1/download_tags/285″,”@type”:”DownloadTag”,”id”:285,”name”:”gate-all-around (GAA)”}],”date”:”2025-11-01T00:00:00+01:00″,”authors”:”K. K. Bhuwalka, O. Baumgartner, H. Wu, L. Hou, G. Rzepa, D. Yakimets, M. Karner, and C. Liu”}