Contact Poly-Pitch Scaling of Si GAA-NSS Down to A10 Node: Role of Nanosheet Thickness and Junction Profile

K. K. Bhuwalka, L. Hung, G. Rzepa, F. Schanovsky, Z. Stanojević, L. Hou, W. Li, M. Kraner, and Z. Yu
Contact-poly-pitch (CPP) scalability of Gate-All-Around-nanosheet (GAA-NS) device is investigated in detail in combination with sheet thickness (Tns) and junction abruptness (δ) both allowing for spacer-thickness (TSP) and gate-length (LG) scaling. Using an extensively calibrated advanced transport model combining with the DTCO flow we account for accurate device and circuit intrinsics and parasitics. We highlight trade-off between Tsp and Lg scaling (Lg scaling better than Tsp); TNs can be scaled to ∼ 3.5 nm maintaining iso-performance allowing for a minimum CPP of ∼ 38 nm (LG ∼ 10 nm). Aggressively improving δ can further scale CPP to ∼ 34 nm (LG ∼ 6 nm), though TNS scaling gain saturates due to severe mobility degradation.
DOI: 10.1109/ESSERC66193.2025.11214041
Publication date: 08 September 2025
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