Inflection Points in GAA NS-FET to C-FET Scaling Considering Impact of DTCO Boosters

{“@id”:”/api/v1/downloads/3345″,”@type”:”Download”,”id”:3345,”title”:”Inflection Points in GAA NS-FET to C-FET Scaling Considering Impact of DTCO Boosters”,”filename”:”IEEE-2024_Inflection-Points-in-GAA-NS-FET-to-C-FET-Scaling-Considering-Impact-of-DTCO-Boosters”,”abstract”:”Complimentary FETs (C-FETs) enable aggressive standard cell height reduction, facilitating on-target area scaling without shrinking contacted gate pitch (CGP). We extensively benchmark nanosheet (NS)-based C-FET s against gate-all-around (GAA) NS FETs across range of metal pitches (MPs) tracking their power, performance, and area (PPA). The impact of back-end of line (BEoL) RC, new materials, and various device boosters is further explored. Four-track C-FET designed with 20-nm MP offers 62% smaller area and provides 28% extra speed at isopower (S@P) over reference NS-FET device.”,”level”:null,”doi”:”10.1109/TED.2024.3368380″,”status”:”published”,”remarks”:”CoAuthor: G. Rzepa”,”files”:[{“@type”:”File”,”id”:29631,”name”:”IEEE-2024_Inflection-Points-in-GAA-NS-FET-to-C-FET-Scaling-Considering-Impact-of-DTCO-Boosters.nofile”,”bytes”:0}],”tags”:[{“@id”:”/api/v1/download_tags/20″,”@type”:”DownloadTag”,”id”:20,”name”:”publication”},{“@id”:”/api/v1/download_tags/209″,”@type”:”DownloadTag”,”id”:209,”name”:”Logic gates”},{“@id”:”/api/v1/download_tags/238″,”@type”:”DownloadTag”,”id”:238,”name”:”Microprocessors”},{“@id”:”/api/v1/download_tags/240″,”@type”:”DownloadTag”,”id”:240,”name”:”Computer architecture”},{“@id”:”/api/v1/download_tags/279″,”@type”:”DownloadTag”,”id”:279,”name”:”Business process re-engineering”},{“@id”:”/api/v1/download_tags/280″,”@type”:”DownloadTag”,”id”:280,”name”:”Standards”},{“@id”:”/api/v1/download_tags/281″,”@type”:”DownloadTag”,”id”:281,”name”:”Metals”},{“@id”:”/api/v1/download_tags/282″,”@type”:”DownloadTag”,”id”:282,”name”:”Wires”},{“@id”:”/api/v1/download_tags/283″,”@type”:”DownloadTag”,”id”:283,”name”:”Complimentary FET (C-FET)”},{“@id”:”/api/v1/download_tags/284″,”@type”:”DownloadTag”,”id”:284,”name”:”design-technology co-optimization (DTCO)”},{“@id”:”/api/v1/download_tags/285″,”@type”:”DownloadTag”,”id”:285,”name”:”gate-all-around (GAA)”},{“@id”:”/api/v1/download_tags/286″,”@type”:”DownloadTag”,”id”:286,”name”:”nanosheet (NS)”},{“@id”:”/api/v1/download_tags/287″,”@type”:”DownloadTag”,”id”:287,”name”:”scaling”}],”date”:”2024-04-12T00:00:00+02:00″,”authors”:”Dmitry Yakimets, Krishna K. Bhuwalka, Hao Wu, Gerhard Rzepa, Markus Karner, and Changze Liu”}