Contacted-Poly-Pitch (CPP) Scaling Limitations of Si Gate-All-Around Nanosheet (GAA-NS) Devices
Contacted-poly-pitch (CPP) scalability of gate-all-around (GAA) nanosheet (NS) device is investigated in detail. Combination of NS thickness (TNS) and junction abruptness (δ) allow for spacer thickness (TSP) and gate-length (LG) scaling. Contact-length LCNT scaling does not affect intrinsic performance, but scaling is limited by middle-of-line and interface resistivity. Using an extensively calibrated advanced transport model combined with the transistor design-technology co-optimization (DTCO) flow we account for accurate device and circuit intrinsics and parasitics. We highlight the trade-off between TSP and LG scaling whereby LG can be scaled more aggressively if TSP can be relaxed. TNS can be scaled to ∼ 3.5 nm maintaining iso-performance allowing for a minimum CPP of ∼ 38 nm at LG ∼ 10 nm. Aggressively improving δ can further allow CPP scaling to ∼ 34 nm (LG ∼ 6 nm), though TNS scaling gain saturates due to severe transport degradation.
Publication date: 07 October 2025
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