Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors

Lucas Réveil, Chhandak Mukherjee, Cristell Maneux, Marina Deng, François Marc, Abhishek Kumar, Aurélie Lecestre, Guilhem Larrieu, Arnaud Poittevin, Ian O’Connor, Oskar Baumgartner, and David Pirker
Vertical Nanowire Junction-less Transistors (VN-WFET) are a promising technology for designing energy-efficient neural networks. This work presents the first results for 3D VNWFET logic cell design taking into account the influence of intra-cell parasitic interconnects on circuit performances. The proposed methodology is used to investigate the performance of a CMOS inverter through co-simulation of the VNWFET SPICE compact model coupled with the circuit parasitic netlist extracted from 3D TCAD simulations using a standard circuit simulator.
Publication date: 03 October 2022
Download project (data + PDF)
Simulation files for GTS Framework; < 1 MB
Download PDF

{“@id”:”/api/v1/downloads/3321″,”@type”:”Download”,”id”:3321,”title”:”Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors”,”filename”:”IFIP-2022_Analysis-of-an-Inverter-Logic-Cell-based-on-3D-Vertical-NanoWire-Junction-Less-Transistors”,”abstract”:”Vertical Nanowire Junction-less Transistors (VN-WFET) are a promising technology for designing energy-efficient neural networks. This work presents the first results for 3D VNWFET logic cell design taking into account the influence of intra-cell parasitic interconnects on circuit performances. The proposed methodology is used to investigate the performance of a CMOS inverter through co-simulation of the VNWFET SPICE compact model coupled with the circuit parasitic netlist extracted from 3D TCAD simulations using a standard circuit simulator.”,”level”:null,”doi”:”10.1109/VLSI-SoC54400.2022.9939576″,”status”:”published”,”remarks”:null,”files”:[{“@type”:”File”,”id”:29607,”name”:”IFIP-2022_Analysis-of-an-Inverter-Logic-Cell-based-on-3D-Vertical-NanoWire-Junction-Less-Transistors.nofile”,”bytes”:0}],”tags”:[{“@id”:”/api/v1/download_tags/20″,”@type”:”DownloadTag”,”id”:20,”name”:”publication”},{“@id”:”/api/v1/download_tags/194″,”@type”:”DownloadTag”,”id”:194,”name”:”Semiconductor device modeling”},{“@id”:”/api/v1/download_tags/195″,”@type”:”DownloadTag”,”id”:195,”name”:”Solid modeling”},{“@id”:”/api/v1/download_tags/196″,”@type”:”DownloadTag”,”id”:196,”name”:”Three-dimensional displays”},{“@id”:”/api/v1/download_tags/197″,”@type”:”DownloadTag”,”id”:197,”name”:”Integrated circuit interconnections”},{“@id”:”/api/v1/download_tags/198″,”@type”:”DownloadTag”,”id”:198,”name”:”Very large scale integration”},{“@id”:”/api/v1/download_tags/199″,”@type”:”DownloadTag”,”id”:199,”name”:”SPICE”},{“@id”:”/api/v1/download_tags/200″,”@type”:”DownloadTag”,”id”:200,”name”:”Inverters”},{“@id”:”/api/v1/download_tags/201″,”@type”:”DownloadTag”,”id”:201,”name”:”Junction-less nanowire transistors”},{“@id”:”/api/v1/download_tags/202″,”@type”:”DownloadTag”,”id”:202,”name”:”3D logic cells”},{“@id”:”/api/v1/download_tags/203″,”@type”:”DownloadTag”,”id”:203,”name”:”compact model”},{“@id”:”/api/v1/download_tags/204″,”@type”:”DownloadTag”,”id”:204,”name”:”TCAD simulation”},{“@id”:”/api/v1/download_tags/205″,”@type”:”DownloadTag”,”id”:205,”name”:”parasitic interconnects”}],”date”:”2022-10-03T00:00:00+02:00″,”authors”:”Lucas Réveil, Chhandak Mukherjee, Cristell Maneux, Marina Deng, François Marc, Abhishek Kumar, Aurélie Lecestre, Guilhem Larrieu, Arnaud Poittevin, Ian O’Connor, Oskar Baumgartner, and David Pirker”}