Charge trapping at oxide defects is a prevalent phenomenon in most modern nanoelectronic devices, leading to detrimental reliability issues like bias temperature instability (BTI), trap-assisted tunneling (TAT) or random telegraph noise (RTN). Although these effects are clearly visible in experiments, the microscopic nature of the involved defects remains elusive. However, an in-depth understanding of the underlying atomistic processes and defects responsible for device degradation is key to further improve device reliability. In this work we discuss how insights gained from electrical characterization methods, ab-initio calculations based on density functional theory (DFT), and compact device models can be combined to identify defects near the semiconductor/oxide interface which compromise device reliability.
Publication date: 18 September 2023
Download project (data + PDF)
Simulation files for GTS Framework;
< 1 MB