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DTCO CFET A5 Spice RO – FinFin – ProEmu - Application Example

In this example, an efficient approach for DTCO is demonstrated which combines TCAD with parasitics extraction (PEX), transistor model card extraction, and SPICE simulations. Accurate circuit representations of FinCFET ring oscillators are obtained and their power-performance is analyzed.
Project Name: DTCO_CFET_A5_FinFin_Spice_RO_ProEmu
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{“@id”:”/api/v1/downloads/2824″,”@type”:”Download”,”id”:2824,”title”:”DTCO CFET A5 Spice RO \u2013 FinFin \u2013 ProEmu – Application Example”,”filename”:”DTCO_CFET_A5_FinFin_Spice_RO_ProEmu”,”abstract”:” In this example, an efficient approach for DTCO is demonstrated which combines TCAD with parasitics extraction (PEX), transistor model card extraction, and SPICE simulations. Accurate circuit representations of FinCFET ring oscillators are obtained and their power-performance is analyzed. “,”level”:3,”doi”:null,”status”:”published”,”remarks”:null,”files”:[{“@type”:”File”,”id”:24063,”name”:”DTCO_CFET_A5_FinFin_Spice_RO_ProEmu.pdf”,”bytes”:1184346},{“@type”:”File”,”id”:24064,”name”:”DTCO_CFET_A5_FinFin_Spice_RO_ProEmu.png”,”bytes”:27089},{“@type”:”File”,”id”:24065,”name”:”DTCO_CFET_A5_FinFin_Spice_RO_ProEmu.zip”,”bytes”:1530048038}],”tags”:[{“@id”:”/api/v1/download_tags/16″,”@type”:”DownloadTag”,”id”:16,”name”:”doe”},{“@id”:”/api/v1/download_tags/18″,”@type”:”DownloadTag”,”id”:18,”name”:”dtco”},{“@id”:”/api/v1/download_tags/23″,”@type”:”DownloadTag”,”id”:23,”name”:”example”},{“@id”:”/api/v1/download_tags/32″,”@type”:”DownloadTag”,”id”:32,”name”:”finfet”},{“@id”:”/api/v1/download_tags/73″,”@type”:”DownloadTag”,”id”:73,”name”:”layout to circuit”},{“@id”:”/api/v1/download_tags/74″,”@type”:”DownloadTag”,”id”:74,”name”:”parasitics extraction”},{“@id”:”/api/v1/download_tags/114″,”@type”:”DownloadTag”,”id”:114,”name”:”TutExaCat-Area: DTCO / Technology to Design”},{“@id”:”/api/v1/download_tags/115″,”@type”:”DownloadTag”,”id”:115,”name”:”TutExaCat-Appl.: DTCO, Cell/Circuit Optimization”},{“@id”:”/api/v1/download_tags/118″,”@type”:”DownloadTag”,”id”:118,”name”:”TutExaCat-Tool: GTS Cell Designer”},{“@id”:”/api/v1/download_tags/154″,”@type”:”DownloadTag”,”id”:154,”name”:”TutExaCat-Tool: GTS ProEmu”},{“@id”:”/api/v1/download_tags/155″,”@type”:”DownloadTag”,”id”:155,”name”:”proemu”},{“@id”:”/api/v1/download_tags/172″,”@type”:”DownloadTag”,”id”:172,”name”:”TutExaPrio-0″},{“@id”:”/api/v1/download_tags/180″,”@type”:”DownloadTag”,”id”:180,”name”:”release-gts-2025-03″}],”date”:”2025-08-27T00:00:00+02:00″,”authors”:null}