We propose the architecture and manufacturing process of 6 surrounding-gate-transistor (SGT) SRAM cell for the 1.5nm technology node. The staggered layout and self-aligned patternings have successfully realized a transition from 5nm to 1.5nm node with the same SGT diameter. Electrical characteristics by TCAD simulation are finally demonstrated.
Publication date: 16 May 2021
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Simulation files for GTS Framework;
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