Let Your Memory Lead You
(Andrew Lloyd Webber / Trevor Nunn, Cats)
Every CPU relies on the attached memory, in multiple ways.
Memory is a key component in every computing application – for computation as well as data storage. Its performance, power consumption and reliability are defining specifications for the overall system.
3D Gate All-Around Vertical NAND Flash Memory
Trapping-based non-volatile memories (NVM) have developed into a central building block of modern data storage technology in recent years. The most dominant implementation of this technology today is cylindrical 3D gate all-around vertical NAND (VNAND) structures. Modeling these devices poses a challenge due to the imperfect re-crystallization of the silicon layer during production. This imperfect re-crystallization leads to the formation of multiple grains in the conducting layer which strongly impact the transconductive behavior.
GTS Framework is used at the forefront of V-NAND technology development. The software package offers automated workflows for the generation of realistic grain structures and a sophisticated combination of physical models that has been refined and verified by detailed comparison to experimental data. GTS also offers ready-to-run configurable examples for the simulation of common experimental setups, e.g. transconductance behavior, retention, write/erase, and ISPP, of full 3D multi-gate V-NAND structures.
The transconductance of V-NAND devices shows complex device-to-device variability. This variability originates from the formation of silicon grains with varying crystal orientation in the conducting channel layer of the macaroni structure as well as from discrete traps.
Sophisticated modeling is used to explain the state-of-the-art experimental observations on V-NAND structures. The dependence of the carrier mobility on the grain orientation, mechanical stress, and gate bias, as well as increased scattering at the grain boundaries are considered to accurately model the on-current variability. Barrier hopping at the grain boundary is used to explain the temperature dependence of the on-state current when grains are present. Discrete traps at the grain boundaries are included to model the sub-threshold swing degradation.
Time-zero-variability as well as time dependent variability are captured in the physical models of GTS Minimos-NT and can be conveniently used in large scale statistical studies using the infrastructure provided by GTS Framework.
Random Telegraph Noise
In addition to impacting the transconductance behavior, the charging and discharging of point defects in the poly-grain channel gives rise to random telegraph signals that impact the readout reliability of the devices. The GTS 3D TCAD simulator can efficiently determine the regions of increased vulnerability to traps in a device using a linear response method. It has been successfully used to model and explain large single-trap charge-induced VT-shifts obtained by measurements of GAA-VNAND devices.
GTS Software is actively used for the simulation of the charging dynamics of flash memory technologies, both state-of-the-art and path-finding. GTS Minimos-NT offers physical models for various charge storage layers, including simple metal floating gates, NOR Flash polysilicon layers, and SONOS trapping layers.
Quantum mechanical tunneling through insulators can be calculated on realistic complex 3D geometries using the flexible and robust tunnel path placement algorithms.
GTS Minimos-NT features a state-of-the art dedicated model set for SONOS charge trapping layer dynamics consisting of
- a description of the free carrier motion in the trapping layer as a field-dependent hopping transport
- a non-uniform distribution of electrically active traps inside the trapping layer
- a dedicated trap to band tunneling emission model
Using this model set, GTS Framework quantitatively predicts experimental ISPP, ISPE, and retention data with one common parameter set, accurately capturing the dependence of the program dynamics on the voltage of the control gate.
Transconductance and charge trapping layer models can be combined with versatile and predictive oxide degradation models (insulator charging at point defects, trap-assisted tunneling) to describe non-ideal effects including increased retention loss and charge accumulation in the tunnel oxide. For the analysis of time-dependent variability and single-events, GTS Framework offers an advanced kinetic Monte Carlo engine.
DRAM cells are today’s most important volatile memory technology and are found in every computing device. As the information in DRAM cells is stored capacitively, the cell transistors have to fulfill very tight specifications with respect to off-state leakage.
Design and Optimization of DRAM Cell Transistors
GTS Framework provides a fast and efficient solution for the design and optimization of high-speed and low-power DRAM cell transistors. Easy-to-use structure templates are available for the generation of state-of-the-art cell transistor geometries, e.g. the saddle-fin structure.
GTS Minimos-NT offers simulation models for storage node leakage (SN LKG) as a function of doping, temperature, gate work-function, and bias conditions. Reverse junction leakage is modeled by Shockley-Read-Hall (SRH) bulk traps including the field enhancement effect. By using discrete traps, statistical properties of the junction leakage can be described.
Gate-induced drain leakage (GIDL) is calculated accurately using quantum mechanical tunneling models on leakage paths through the oxide. The tunneling paths are placed fully automatically to capture the DRAM’s complex geometry. The predictions can be used to meet off-leakage control in order to reduce the refresh time.
GTS tools allow the calculation of operation current (Iop). The effect of discrete random traps and dopants can be simulated statistically, which in few cases may result in significant on-current reduction. Quantum confinement can be incorporated by standard density gradient (DG) quantum correction or by a full solution of the Schrödinger equation. Short channel effects (SCE) are included by proper calibration against SB-BTE simulation results from GTS Nano Device Simulator (NDS). The simulations are used to target drain-induced barrier lowering (DIBL), sub-threshold swing and trans-conductance for superior current-drive ability.
Although ferroelectric memories have been commercially available for a while, recent breakthroughs stand to put it back into the limelight compared to flash. Looking into the near future, ferroelectric memory is potentially at a precipice of new interest and design challenges.
The suggestion of a ferroelectric memory based on a simpler, more compact MOSFET stands to reduce the size of the device. The recent finding that hafnium oxide, which is the oxide of choice that is already in use in standard semiconductor manufacturing, becomes ferroelectric when it is sufficiently thinned is considered revolutionary. These two discoveries taken in concert potentially allow for a new ferroelectric memory made of a single transistor compatible with standard CMOS manufacturing.
TCAD tools capturing the relevant ferroelectric properties will be essential to guide these exciting new developments – we are convinced you will find GTS Minimos-NT to be an ideal one.
GTS Minimos NT – simulate semiconductor devices and circuits: Run steady-state, transient, and small-signal analysis of arbitrary 2D and 3D device geometries. Combine multiple devices in a circuit with compact models. Run thermal analysys of devices and circuits.
GTS Nano Device Simulator – the first complete solution for effective physical simulation of nano-devices across technology nodes. Get profound predictive data for new materials and device architectures.
GTS Framework – the solid base of all GTS products and your working environment. Includes device editing, file management, distributed job execution, visualization, post-processing, a Python interface, etc.