This example demonstrates the usage of the GTS Nano Device Simulator to model n-type and p-type bulk FinFETs.

Usage of GTS Nano Device Simulator to model nMOS gate-all-around FinFET transistors: We show Id,lin, Id,sat, extraction of MOS parameters; effects of varying gate length, channel orientation, mechanical stress.

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In this example we investigate the effects of mechanical stress in a PMOS FinFET with SiGe Source/Drain Epi layers using GTS VSP and GTS MINIMOS-NT.

This example demonstrates the use of oxide defects in stationary and in transient simulations. The device under test is a 3D planar pMOS device based on the template database of the GTS Framework.

Demonstration of the hot-carrier degradation model implemented in the GTS Framework.

Minimos-NT simulations obeying the atomistic nature of traps and dopants. Based on a FinFET, the influence of discrete interface and oxide traps as well as discrete dopants on the device characteristics are illustrated.

Basic simulation flow demonstrated on an SOI FinFET. Template based structure generation and different Minimos-NT simulation models, such as Drift Diffusion and Density Gradient.

This example illustrates the simulation of heavy ion impact events in CMOS structures using GTS Framework.

Static and transient analysis of CMOS structures. Starting with single transistors, the complexity is increased up to a full 6-transistor SRAM cell, including the transient simulation of a full write cycle.

SiC4H Schottky Barrier Diode, including Impact Ionization Model and Auger Recombination.

SiC vertical DMOS - breakthrough, snapback, electron current density

This example demonstrates the simulation of SiC devices on the example of a MESFET, including self heating effects.

Simulation of GaN devices on the example of a High electron mobility Transistor