Global TCAD Solutions

Cutting-Edge TCAD



Events and Latest Developments at GTS

Please find below the newest and past releases of or our corporate news.

RSS Feed

We would love to inform you about relevant events and developments at GTS,
and welcome you to subscribe to our RSS newsfeed.
(We keep distortion to a minimum, not releasing more than ca. 12 items per year.)


IEDM 2018, MOS-AK Workshop in San Francisco

Visit the GTS booth in the IEDM exhibits area and join our presentation at MOS-AK workshop on Dec 5


GTS Framework 2018.09

New applications: TCAD in DTCO, self-heating (SH) simulation for logic cells, germanium gate-all-around architectures (GAA)


TCAD in DTCO: Cell Designer - GTS Paper @ ESSDERC 2018

GTS presenting first practical TCAD-based work flow for design-technology co-optimization (DTCO) of standard cells.


NC-FET, FeRAM: GTS @ VLSI and NCFET Research Grant

Next to its contribution at VLSI/SNW 2018, GTS takes part in a FFG research project to create a 3D TCAD model for ferroelectric materials.


V-NAND application example: Channel trans-conductance

Modeling and simulation of V-NAND poly-silicon channel trans-conductance, including variability


GTS @ EuroSOI-ULIS 2018: Scaling limits of FD-SOI

Presenting a Physical Modeling Study Based on 3D Phase-Space Subband Boltzmann Transport for Fully-Depleted SOI Technology


GTS Framework 2018.03

New applications: V-NAND transconductance variability, physical simulation of FD-SOI technology


GTS @ IEDM 2017: Cell Simulation, DTCO

Visit the GTS booth in the IEDM exhibits area to learn about our latest products and developments!


Service Point in Taiwan R.O.C.

Introducing GTS local representative for East Asia


Listed by European Commission Innovation Radar 2017

GTS was identified as one of the top 10 "Best Young SME" by the European Commission Innovation Radar 2017.


IEEE EDS Delhi Workshop, AICTE / IIT(BHU) Varanasi

GTS workshops at two events in India, coordinated by our partner TNL.


New GTS Partner in India

TechNextLab becoming GTS partner for distribution and support in India.


IWRMN-EDHE 2017 Invited Talk: From Impact to Upset

Physical Modeling of Irradiation Effects in nano-scaled CMOS Logic and Memory Devices


Join our event at VLSI-TSA: DTCO for Advanced Nodes

Towards Physics-based DTCO for N7 and sub-N7 Technologies


GTS @ VLSI-TSA Symposium Hsinchu, Taiwan

TCAD-Based Characterization of Logic Cells: Power, Performance, Area, and Variability


GTS @ 12th ESA Geant4 Space Users Workshop

GTS presenting TCAD modeling toolchain for irradition effects in nano-scale CMOS logic devices using layout-based design


IMEC Course: Advanced TCAD for sub-N7 FinFETs & Nanowires

GTS giving course at IMEC academy on march 29-30, 2017.Included is a hands-on session with multiple topics in the field of advanced CMOS simulation.


SISPAD 2016 Best Paper Award: GTS among Top Three

GTS' paper 04.1 "Phase-Space Solution of the Subband Boltzmann Transport Equation for Nano-Scale TCAD" was ranked on third place.


Identifying Crucial Aspects for Stacked NW FET - IEDM 2016

In their 2016 IEDM paper, GTS scientists present latest results with direct implications on upcoming nanowire technologies.


GTS @ SISPAD 2016: SB-BTE for Nano-Scale CMOS

CTO presenting GTS' unique and robust combination of SB-BTE, DD and Poisson approaches for reliable predictions of device performance