GTS Framework offers an accurate yet efficient model to predict and also "design" fluctuations in the electrical device characteristics. Mixed-mode analysis allows for investigation of circuits, such as 6T or 8T SRAM cells. The GTS variability module automatically introduces major/dominant variability sources to the 3D device- and circuit simulation model
Atomistic Traps and Dopants (or Random Dopant Fluctuations)
For simulation of random discrete dopants (RDD) and discrete oxide and interface traps, Minimos-NT is capable of generating random configurations, in order to capture the atomistic nature of traps and dopants [Nobuyuki01]. Random dopant fluctuations are dominant in recent planar CMOS technologies.
See Example: SOI-FinFET-Discr.Dop.
Metal Grain Roughness
The grain roughness model allows to describe poly or metal gate granularity (MGG) and the induced work function fluctuation (WKF). In order to achieve patterns with the desired statistical properties, random surface grains are grown from random seeds to the average size. The WKF due to grain orientations of gate materials such as titanium nitride (TiN), molybdenum nitride (MoN), and tungsten nitride (WN) becomes dominant for undoped channel devices [Cheng10].
Line Edge Roughness
As a further component, the line edge roughness (LER) model allows to introduce geometrical variation to a semiconductor surface or interface [Asenov03]. With its flexible generic implementation, LER can describe variations due to the lithographic process like gate edge roughness (GER) or trench edge roughness, as well as other process-induced fluctuations like oxide thickness variation (OTV). In FinFET structures, fin edge roughness (FER) is another major variability source that can be captured using the LER model.
In order to obtain meaningful statistical values, variability analysis typically requires 100 to 1000 cases (=device implementations). Here, our in-house cluster solution GTS JobServer automates setup and execution of such simulation jobs, including task scheduling, distribution and collection of results. Running simulation tasks can be easily monitored, and intermediate results are instantly accessible at runtime as well as after a job has finished.
GTS Framework offers a range of integrated post-processing functions for calculating characteristic values like threshold voltage, DIBL, ION/IOFF-ratio, sub-threshold slope and more. It allows to extract meaningful statistical results in a homogeneous work-flow within seconds.
Considering the impact of variability sources on device properties is vital to control variability and yield for current and future device generations.
The GTS variability module allows simulation and thorough analysis of various variability sources such as discrete random dopants (RDD), metal grain roughness (MGR), line edge roughness (LER), etc., on device and circuit level.
Example in Detail
For a step-by-step description of an application example, see Variability Simulation.