Global TCAD Solutions

Predictions based on Physics

SiC Vertical DMOS

This example demonstrates the simulation of SiC devices on the example of a vertical DMOS.

ToolFolder 001 contains the vertical DMOS Structure, as shown in Figure 1.

ToolFolder 002 shows the transfer characteristics for different source-drain bias voltages, see Figure 2a. ToolFolder 003 shows the output characteristics, see Figure 2b.

Figure 3 shows the electric field in the off-state with a drain bias of 100 V. At the edge of the source dopant a high electric field can be seen. This will be the starting point of the breaktrough, which will be discussed later on.

Figure 4 shows the electron current of the switched on device. Because the main direction of the current has to change by at least 90 degrees advances in technology have let to the development of an DMOS with a vertical channel. Such devices can take advantage of the anisotropic properties of the used semiconductor material. For the calculation of the breakthrough / snapback a slightly modified mesh is used (see ToolFolder 004). Because there is no current flow in the channel the usual channel refinement can be omitted saving mesh points and speeding up the simulation.

ToolFolder 005 shows the first part of the breakdown curve calculated with a voltage stepping toward a small current increase in this case 900 Volts.

The successor ToolFolder 006 uses the last step of 005 as initial guess and switches to current stepping. The breakdown curve is shown in Figure 5.

Figure 6 shows the electron current density at different states. The leftmost picture shows the beginning of the breakthrough at the edge of the source dopant at a source-drain voltage of 900 V and a drain current of 0.4 mA/um. The middle picture shows the maximum reached source-drain voltage of approx. 1200 V at a current of 4 mA/um. The right-hand picture shows the formation of a current channel at 10 mA/um resulting in the reduced voltage of approx. 700 V.

This example was created using GTS Framework Release 2016.09. Other releases might need adjustments or have slightly different user interfaces.

 

 

Fig. 1: The structure and net dopant concentration of the vertical DMOS.
Fig. 2: a) Transfer characteristics for different drain voltages. b) Output characteristics
Fig. 3: The electric field in the biased DMOS VDS = 100 V, VGS = 0V
Fig. 4: Electron current density in on state VDS = 100 V, VGS = 30V
Fig. 5: Breakthrough / snapback with Vdrain = 0V
Fig. 6: Electron current density in the breaktrough at drain currents 0.4 mA/um, 4 mA/um and 10 mA/um (same scale for all)