Optimizing an nMOS GAA FET using Nano Device Simulator
This example demonstrates the usage of GTS Nano Device Simulator to model nMOS gate-all-around FinFET transistors. It is implemented in GTS Framework. In a first step, the drain current in linear and saturation regime is calculated using the phase-space formalism of the Boltzmann transport equation. We demonstrate the extraction of relevant MOS parameters. In the advanced part of the tutorial, we investigate the changes in drain current with varying gate lengths. We also take a look at the impact of channel orientation and mechanical stress on the device performance.