Global TCAD Solutions

Predictions based on Physics

Bias Temperature Instability

In this tutorial the basic handling of BTI simulation features is demonstrated.

First, a suitable PMOS transistor will be created based on a template.

Degradation is investigated by a transient simulation of a negative stress Gate voltage phase followed by relaxation conditions. The BTI stress activates trap charges which change the electrostatics of the device and induce a shift of the threshold voltage (Vth). It is calculated in a steady-state simulation before and after stress and relaxation.

Finally, a numerically efficient method to estimate the threshold voltage shift (dVth) by charged traps is introduced. It allows to determine dVth over time without further overhead.

It is assumed that you are already familiar with GTS Framework and the idea of projects and ToolFolders, as explained in the Getting Started tutorial.

This tutorial was created using GTS Framework Release 2013. Other releases might need adjustments or have slightly different user interfaces.