This tutorial demonstrates a typical work-flow for calculating the subband structure of a channel cross-section and the channel’s mobility.

This tutorial shows a simulation of a non-planar transistor, using a GTS-supplied 3D template of an NMOS 20nm nanowire transistor

This tutorial demonstrates the generation of full 3D device simulation models from mask files using the GTS layout-based structure generation function.

In this tutorial, an LDMOS transistor is investigated using different models and simulation modes. First, the influence of geometric variations on the output characteristics is surveyed using GTS Structure device templates.

This tutorial demonstrates a basic work-flow for analyzing FinFET or nanowire cross-sections using VSP.

Will be online soon (please use PDF version for now).

This tutorial demonstrates the basic usage of VSHE by example of simulation of a 50 nm nMOS transistor, based on spherical harmonics expansion.

Will be online soon - please refer to PDF version for now.

In this tutorial the basic handling of BTI simulation features is demonstrated. A suitable PMOS transistor will be created and degradation will be investigated by a transient simulation of stress Gate voltage phase followed by relaxation conditions.

Simulation of a single event response due to heavy ion strikes. Starting from single event transition (SET) investigations on a single transistor, the complexity is increased to a 6T-SRAM single event upset simulation.

This tutorial demonstrates calculation of the fluctuations in the electrical characteristic due to random discrete dopants (RDD) and metal grain roughness (MGR).

This tutorial shows how to run a device simulation with line edge roughness of the gate on the example of a FinFET.