Tutorials guide step-by-step. Begin with Getting Started.
Application Examples mainly focus on the results.
For both, the project folder contains all data.
The graduation caps indicate the sophistication level: introductory / intermediate / advanced.
Click each row for details. To skip the details, click the icons at the right.
Found matches:
Advanced Scripting - Tutorial
This tutorial demonstrates how to use a setup where the Optimizer tool calls the DOE tool to run a more complex optimization with multiple reference data files.
Advanced Scripting - Tutorial
This tutorial demonstrates how to use a setup where the Optimizer tool calls the DOE tool to run a more complex optimization with multiple reference data files.
Band-Edge Stress - Application Example
This example demonstrates the effect of stress on band-edge and as a result, changes in C-V curves.
Band-Edge Stress - Application Example
This example demonstrates the effect of stress on band-edge and as a result, changes in C-V curves.
Band-Edge Stress - Application Example
This example demonstrates the effect of stress on band-edge and as a result, changes in C-V curves.
Band-Edge Stress - Application Example
This example demonstrates the effect of stress on band-edge and as a result, changes in C-V curves.
Bias Temperature Instability - Tutorial
In this tutorial the BTI simulation capabilities of Minimos-NT are presented. Transient simulations on a distributed device are used to show trap charging and threshold voltage degradation at varying stress and relaxation conditions.
Bias Temperature Instability - Tutorial
In this tutorial the BTI simulation capabilities of Minimos-NT are presented. Transient simulations on a distributed device are used to show trap charging and threshold voltage degradation at varying stress and relaxation conditions.
Bias Temperature Instability - Tutorial
In this tutorial the BTI simulation capabilities of Minimos-NT are presented. Transient simulations on a distributed device are used to show trap charging and threshold voltage degradation at varying stress and relaxation conditions.
BTI Simulations with Comphy - Tutorial
This tutorial shows how to use the Comphy module in GTS Framework.
BTI Simulations with Comphy - Tutorial
This tutorial shows how to use the Comphy module in GTS Framework.
BTI Simulations with Comphy - Tutorial
This tutorial shows how to use the Comphy module in GTS Framework.
Carbon Nano Tubes - Application Example
This example demonstrates the simulation of 2D and 3D carbon nano-tube devices. A low-field simulation is done on a back-gated 2D device and PST simulations on 3D back-gate and embedded-gate devices.
Carbon Nano Tubes - Application Example
This example demonstrates the simulation of 2D and 3D carbon nano-tube devices. A low-field simulation is done on a back-gated 2D device and PST simulations on 3D back-gate and embedded-gate devices.
Carbon Nano Tubes - Application Example
This example demonstrates the simulation of 2D and 3D carbon nano-tube devices. A low-field simulation is done on a back-gated 2D device and PST simulations on 3D back-gate and embedded-gate devices.
CMOS Heavy Ion Impact - Application Example
Heavy ion impact events in CMOS structures are investigated by simulation of transient responses of a single transistor, an inverter, an inverter chain and a SRAM cell.
CMOS Heavy Ion Impact - Application Example
Heavy ion impact events in CMOS structures are investigated by simulation of transient responses of a single transistor, an inverter, an inverter chain and a SRAM cell.
CMOS Heavy Ion Impact - Application Example
Heavy ion impact events in CMOS structures are investigated by simulation of transient responses of a single transistor, an inverter, an inverter chain and a SRAM cell.
CMOS Logic - Application Example
Mixed-mode simulation of increasing complexity; starting from single transistors, moving on to a CMOS inverter, and finally reaching the full SRAM cell.
CMOS Logic - Application Example
Mixed-mode simulation of increasing complexity; starting from single transistors, moving on to a CMOS inverter, and finally reaching the full SRAM cell.
Creating LSG Technology Files - Tutorial
This tutorial demonstrates the step-by-step creation of a simple technology file.
Creating LSG Technology Files - Tutorial
This tutorial demonstrates the step-by-step creation of a simple technology file.
Creating LSG Technology Files - Tutorial
This tutorial demonstrates the step-by-step creation of a simple technology file.
Creating LSG Technology Files - Tutorial
This tutorial demonstrates the step-by-step creation of a simple technology file.
Device Editor - Tutorial
This tutorial introduces the device editor integrated in GTS Framework. It illustrates editing device doping profiles as well as 2D and 3D device structures.
Device Editor - Tutorial
This tutorial introduces the device editor integrated in GTS Framework. It illustrates editing device doping profiles as well as 2D and 3D device structures.
Device Editor - Tutorial
This tutorial introduces the device editor integrated in GTS Framework. It illustrates editing device doping profiles as well as 2D and 3D device structures.
Device Simulation - Tutorial
Steady-state Simulations; improve convergence performance by using results from one simulation to initialize next one. Quantum tunnelling through oxide, Gate currents for varying Drain voltages.
Device Simulation - Tutorial
Steady-state Simulations; improve convergence performance by using results from one simulation to initialize next one. Quantum tunnelling through oxide, Gate currents for varying Drain voltages.
Device Simulation - Tutorial
Steady-state Simulations; improve convergence performance by using results from one simulation to initialize next one. Quantum tunnelling through oxide, Gate currents for varying Drain voltages.
DOE Table from File - Tutorial
This tutorial demonstrates how to read the Design of Experiment table from a file. This allows you to customize the DOE manually or generate it by an external tool.
DOE Table from File - Tutorial
This tutorial demonstrates how to read the Design of Experiment table from a file. This allows you to customize the DOE manually or generate it by an external tool.
DOE, Optimizer, Post-Processing - Tutorial
This tutorial demonstrates the design-of-experiments (DOE) and parameter-fitting capabilities (optimizer) of GTS Framework. Further, it illustrates usage of the post-processing tool to show the influence of a device parameter on specific figures of merit of a MOSFET, such as Vth, ION, IOFF, and the sub-threshold slope.
DOE, Optimizer, Post-Processing - Tutorial
This tutorial demonstrates the design-of-experiments (DOE) and parameter-fitting capabilities (optimizer) of GTS Framework. Further, it illustrates usage of the post-processing tool to show the influence of a device parameter on specific figures of merit of a MOSFET, such as Vth, ION, IOFF, and the sub-threshold slope.
DOE, Optimizer, Post-Processing - Tutorial
This tutorial demonstrates the design-of-experiments (DOE) and parameter-fitting capabilities (optimizer) of GTS Framework. Further, it illustrates usage of the post-processing tool to show the influence of a device parameter on specific figures of merit of a MOSFET, such as Vth, ION, IOFF, and the sub-threshold slope.
DTCO Based on CFET Full Cell RO - Application Example
In this example, a computationally expensive but accurate DTCO flow is demonstrated which employs TCAD simulations of full ring oscillator cells in CFET technology.
DTCO Based on CFET Full Cell RO - Application Example
In this example, a computationally expensive but accurate DTCO flow is demonstrated which employs TCAD simulations of full ring oscillator cells in CFET technology.
DTCO Based on CFET Full Cell RO - Application Example
In this example, a computationally expensive but accurate DTCO flow is demonstrated which employs TCAD simulations of full ring oscillator cells in CFET technology.
DTCO Based on Full Cell RO - Application Example
A computationally expensive but accurate DTCO flow is demonstrated which employs TCAD simulations of full ring oscillator cells in FinFET technology.
DTCO Based on Full Cell RO - Application Example
A computationally expensive but accurate DTCO flow is demonstrated which employs TCAD simulations of full ring oscillator cells in FinFET technology.
DTCO Based on Full Cell RO - Application Example
A computationally expensive but accurate DTCO flow is demonstrated which employs TCAD simulations of full ring oscillator cells in FinFET technology.
DTCO Based on Nanosheet Full Cell RO - Application Example
In this example, a computationally expensive but accurate DTCO flow is demonstrated which employs TCAD simulations of full ring oscillator cells in nanosheet technology.
DTCO Based on Nanosheet Full Cell RO - Application Example
In this example, a computationally expensive but accurate DTCO flow is demonstrated which employs TCAD simulations of full ring oscillator cells in nanosheet technology.
DTCO Based on Nanosheet Full Cell RO - Application Example
In this example, a computationally expensive but accurate DTCO flow is demonstrated which employs TCAD simulations of full ring oscillator cells in nanosheet technology.
DTCO Based on RC Analysis - Application Example
In this example, an efficient approach for DTCO of FinFET technology is demonstrated which combines FEOL transistor simulations and BEOL parasitics extraction (PEX) of inverter cells.
DTCO Based on RC Analysis - Application Example
In this example, an efficient approach for DTCO of FinFET technology is demonstrated which combines FEOL transistor simulations and BEOL parasitics extraction (PEX) of inverter cells.
DTCO Based on RC Analysis - Application Example
In this example, an efficient approach for DTCO of FinFET technology is demonstrated which combines FEOL transistor simulations and BEOL parasitics extraction (PEX) of inverter cells.
DTCO Based on RC Analysis - Application Example
In this example, an efficient approach for DTCO of FinFET technology is demonstrated which combines FEOL transistor simulations and BEOL parasitics extraction (PEX) of inverter cells.
DTCO Based on RC Analysis of Complementary FETs - Application Example
In this example, an efficient approach for DTCO of CFET technologies is demonstrated which combines FEOL transistor simulations and MEOL/BEOL paracitics extraction (PEX) of inverter cells.
DTCO Based on RC Analysis of Complementary FETs - Application Example
In this example, an efficient approach for DTCO of CFET technologies is demonstrated which combines FEOL transistor simulations and MEOL/BEOL paracitics extraction (PEX) of inverter cells.
DTCO Based on RC Analysis of Complementary FETs - Application Example
In this example, an efficient approach for DTCO of CFET technologies is demonstrated which combines FEOL transistor simulations and MEOL/BEOL paracitics extraction (PEX) of inverter cells.
DTCO FinFET N7 Reliability Post Minimos BTI - Application Example
In this example, the compact-physics simulator Comphy is integrated in a TCAD flow to simulate the reliability of FETs under 10 years of AC operation. The full accuracy of 3D TCAD is maintained for the efficient calculations of the transient charging and discharging of the defects in the oxides and at the interfaces.
DTCO FinFET N7 Reliability Post Minimos BTI - Application Example
In this example, the compact-physics simulator Comphy is integrated in a TCAD flow to simulate the reliability of FETs under 10 years of AC operation. The full accuracy of 3D TCAD is maintained for the efficient calculations of the transient charging and discharging of the defects in the oxides and at the interfaces.
DTCO FinFET N7 Reliability Post Minimos BTI - Application Example
In this example, the compact-physics simulator Comphy is integrated in a TCAD flow to simulate the reliability of FETs under 10 years of AC operation. The full accuracy of 3D TCAD is maintained for the efficient calculations of the transient charging and discharging of the defects in the oxides and at the interfaces.
DTCO FinFET N7 Reliability Post Minimos BTI - Application Example
In this example, the compact-physics simulator Comphy is integrated in a TCAD flow to simulate the reliability of FETs under 10 years of AC operation. The full accuracy of 3D TCAD is maintained for the efficient calculations of the transient charging and discharging of the defects in the oxides and at the interfaces.
DTCO FinFET N7 Spice Model Extractor - Application Example
In this example, device simulations and PEX of FinFETs are conducted to extract their nominal BSIM-CMG SPICE model cards. Additionally, it is demonstrated how to incorporate variability sources to extract and extrapolate variability model cards.
DTCO FinFET N7 Spice Model Extractor - Application Example
In this example, device simulations and PEX of FinFETs are conducted to extract their nominal BSIM-CMG SPICE model cards. Additionally, it is demonstrated how to incorporate variability sources to extract and extrapolate variability model cards.
DTCO FinFET N7 Spice Model Extractor - Application Example
In this example, device simulations and PEX of FinFETs are conducted to extract their nominal BSIM-CMG SPICE model cards. Additionally, it is demonstrated how to incorporate variability sources to extract and extrapolate variability model cards.
DTCO FinFET N7 Spice Model Extractor - Application Example
In this example, device simulations and PEX of FinFETs are conducted to extract their nominal BSIM-CMG SPICE model cards. Additionally, it is demonstrated how to incorporate variability sources to extract and extrapolate variability model cards.
DTCO FinFET N7 Spice RO - Application Example
In this example, an efficient approach for DTCO is demonstrated which combines TCAD with parasitics extraction (PEX), transistor model card extraction, and SPICE simulations. Accurate circuit representations of FinFET ring oscillators are obtained and their power-performance is analyzed.
DTCO FinFET N7 Spice RO - Application Example
In this example, an efficient approach for DTCO is demonstrated which combines TCAD with parasitics extraction (PEX), transistor model card extraction, and SPICE simulations. Accurate circuit representations of FinFET ring oscillators are obtained and their power-performance is analyzed.
DTCO FinFET N7 Spice RO - Application Example
In this example, an efficient approach for DTCO is demonstrated which combines TCAD with parasitics extraction (PEX), transistor model card extraction, and SPICE simulations. Accurate circuit representations of FinFET ring oscillators are obtained and their power-performance is analyzed.
DTCO FinFET N7 Spice RO - Application Example
In this example, an efficient approach for DTCO is demonstrated which combines TCAD with parasitics extraction (PEX), transistor model card extraction, and SPICE simulations. Accurate circuit representations of FinFET ring oscillators are obtained and their power-performance is analyzed.
DTCO FinFET N7 Spice RO with Var. and Rel. - Application Example
In this example, PEX of inverter cells in FinFET technology are conducted to obtain their full SPICE netlists. Together with the corresponding transistor model cards, these netlists are used for accurate and fast simulation of RO KPIs including variability (RDD, MGG, and geometrical) and reliability (oxide degradation).
DTCO FinFET N7 Spice RO with Var. and Rel. - Application Example
In this example, PEX of inverter cells in FinFET technology are conducted to obtain their full SPICE netlists. Together with the corresponding transistor model cards, these netlists are used for accurate and fast simulation of RO KPIs including variability (RDD, MGG, and geometrical) and reliability (oxide degradation).
DTCO FinFET N7 Spice RO with Var. and Rel. - Application Example
In this example, PEX of inverter cells in FinFET technology are conducted to obtain their full SPICE netlists. Together with the corresponding transistor model cards, these netlists are used for accurate and fast simulation of RO KPIs including variability (RDD, MGG, and geometrical) and reliability (oxide degradation).
DTCO FinFET N7 Spice RO with Var. and Rel. - Application Example
In this example, PEX of inverter cells in FinFET technology are conducted to obtain their full SPICE netlists. Together with the corresponding transistor model cards, these netlists are used for accurate and fast simulation of RO KPIs including variability (RDD, MGG, and geometrical) and reliability (oxide degradation).
DTCO FinFET N7 Spice RO with Var. and Rel. - Application Example
In this example, PEX of inverter cells in FinFET technology are conducted to obtain their full SPICE netlists. Together with the corresponding transistor model cards, these netlists are used for accurate and fast simulation of RO KPIs including variability (RDD, MGG, and geometrical) and reliability (oxide degradation).
DTCO FinFET N7 Spice SRAM - Application Example
In this example, an efficient approach for DTCO is demonstrated which combines TCAD with parasitics extraction (PEX), transistor model card extraction, and SPICE simulations. Accurate circuit representations of FinFET SRAM cells are obtained and their performance is analyzed.
DTCO FinFET N7 Spice SRAM - Application Example
In this example, an efficient approach for DTCO is demonstrated which combines TCAD with parasitics extraction (PEX), transistor model card extraction, and SPICE simulations. Accurate circuit representations of FinFET SRAM cells are obtained and their performance is analyzed.
DTCO FinFET N7 Spice SRAM - Application Example
In this example, an efficient approach for DTCO is demonstrated which combines TCAD with parasitics extraction (PEX), transistor model card extraction, and SPICE simulations. Accurate circuit representations of FinFET SRAM cells are obtained and their performance is analyzed.
DTCO FinFET N7 Spice SRAM - Application Example
In this example, an efficient approach for DTCO is demonstrated which combines TCAD with parasitics extraction (PEX), transistor model card extraction, and SPICE simulations. Accurate circuit representations of FinFET SRAM cells are obtained and their performance is analyzed.
DTCO FinFET N7 Spice SRAM - Application Example
In this example, an efficient approach for DTCO is demonstrated which combines TCAD with parasitics extraction (PEX), transistor model card extraction, and SPICE simulations. Accurate circuit representations of FinFET SRAM cells are obtained and their performance is analyzed.
DTCO FinFET N7 Spice SRAM with Variability - Application Example
In this example, a PEX of SRAM cells in FinFET technology is conducted to obtain the full SPICE netlist. Together with the corresponding transistor model cards, this netlist is used for accurate and fast simulation of SRAM KPIs including variability (RDD, MGG, and geometrical).
DTCO FinFET N7 Spice SRAM with Variability - Application Example
In this example, a PEX of SRAM cells in FinFET technology is conducted to obtain the full SPICE netlist. Together with the corresponding transistor model cards, this netlist is used for accurate and fast simulation of SRAM KPIs including variability (RDD, MGG, and geometrical).
DTCO FinFET N7 Spice SRAM with Variability - Application Example
In this example, a PEX of SRAM cells in FinFET technology is conducted to obtain the full SPICE netlist. Together with the corresponding transistor model cards, this netlist is used for accurate and fast simulation of SRAM KPIs including variability (RDD, MGG, and geometrical).
DTCO FinFET N7 Spice SRAM with Variability - Application Example
In this example, a PEX of SRAM cells in FinFET technology is conducted to obtain the full SPICE netlist. Together with the corresponding transistor model cards, this netlist is used for accurate and fast simulation of SRAM KPIs including variability (RDD, MGG, and geometrical).
DTCO FinFET N7 Spice SRAM with Variability - Application Example
In this example, a PEX of SRAM cells in FinFET technology is conducted to obtain the full SPICE netlist. Together with the corresponding transistor model cards, this netlist is used for accurate and fast simulation of SRAM KPIs including variability (RDD, MGG, and geometrical).
DTCO FinFET N7 Spice SRAM with Variability - Application Example
In this example, a PEX of SRAM cells in FinFET technology is conducted to obtain the full SPICE netlist. Together with the corresponding transistor model cards, this netlist is used for accurate and fast simulation of SRAM KPIs including variability (RDD, MGG, and geometrical).
DTCO NS N3 Spice Model Extractor - Application Example
In this example, device simulations and PEX of nanosheet FETs are conducted to extract their nominal BSIM-CMG SPICE model cards. Additionally, it is demonstrated how to incorporate variability sources to extract and extrapolate variability model cards.
DTCO NS N3 Spice Model Extractor - Application Example
In this example, device simulations and PEX of nanosheet FETs are conducted to extract their nominal BSIM-CMG SPICE model cards. Additionally, it is demonstrated how to incorporate variability sources to extract and extrapolate variability model cards.
DTCO NS N3 Spice Model Extractor - Application Example
In this example, device simulations and PEX of nanosheet FETs are conducted to extract their nominal BSIM-CMG SPICE model cards. Additionally, it is demonstrated how to incorporate variability sources to extract and extrapolate variability model cards.
DTCO NS N3 Spice Model Extractor - Application Example
In this example, device simulations and PEX of nanosheet FETs are conducted to extract their nominal BSIM-CMG SPICE model cards. Additionally, it is demonstrated how to incorporate variability sources to extract and extrapolate variability model cards.
DTCO NS N3 Spice Model Extractor - Application Example
In this example, device simulations and PEX of nanosheet FETs are conducted to extract their nominal BSIM-CMG SPICE model cards. Additionally, it is demonstrated how to incorporate variability sources to extract and extrapolate variability model cards.
DTCO Spice RO using CFET – FinFin - Application Example
An efficient approach for DTCO is demonstrated which combines parasitics extraction (PEX), BSIM model card extraction, and SPICE simulations of ring oscillators in CFET/FinFin technology. There is an analogous example for NsNs.
DTCO Spice RO using CFET – NsNs - Application Example
An efficient approach for DTCO is demonstrated which combines parasitics extraction (PEX), BSIM model card extraction, and SPICE simulations of ring oscillators in CFET/NsNs technology. There is an analogous example for FinFin.
DTCO Spice RO using CFET – NsNs - Application Example
An efficient approach for DTCO is demonstrated which combines parasitics extraction (PEX), BSIM model card extraction, and SPICE simulations of ring oscillators in CFET/NsNs technology. There is an analogous example for FinFin.
DTCO Spice RO using CFET – NsNs - Application Example
An efficient approach for DTCO is demonstrated which combines parasitics extraction (PEX), BSIM model card extraction, and SPICE simulations of ring oscillators in CFET/NsNs technology. There is an analogous example for FinFin.
DTCO Spice RO using CFET – NsNs - Application Example
An efficient approach for DTCO is demonstrated which combines parasitics extraction (PEX), BSIM model card extraction, and SPICE simulations of ring oscillators in CFET/NsNs technology. There is an analogous example for FinFin.
Ferroelectric Capacitors and Models - Application Example
A series of studies on a ferroelectric capacitor designed to introduce the Monte Carlo (MC) based ferroelectric models available within the GTS Framework
Ferroelectric Capacitors and Models - Application Example
A series of studies on a ferroelectric capacitor designed to introduce the Monte Carlo (MC) based ferroelectric models available within the GTS Framework
Ferroelectric Capacitors and Models - Application Example
A series of studies on a ferroelectric capacitor designed to introduce the Monte Carlo (MC) based ferroelectric models available within the GTS Framework
Ferroelectric Capacitors and Models - Application Example
A series of studies on a ferroelectric capacitor designed to introduce the Monte Carlo (MC) based ferroelectric models available within the GTS Framework
Ferroelectrics - Tutorial
This tutorial shows how to run device simulations with ferroelectric materials. We examine a capacitor with ferroelectric material, hysteresis by using the model evaluation mode, and a MOSFET with a gate stack using a ferroelectric material.
Ferroelectrics - Tutorial
This tutorial shows how to run device simulations with ferroelectric materials. We examine a capacitor with ferroelectric material, hysteresis by using the model evaluation mode, and a MOSFET with a gate stack using a ferroelectric material.
Ferroelectrics - Tutorial
This tutorial shows how to run device simulations with ferroelectric materials. We examine a capacitor with ferroelectric material, hysteresis by using the model evaluation mode, and a MOSFET with a gate stack using a ferroelectric material.
Ferroelectrics - Tutorial
This tutorial shows how to run device simulations with ferroelectric materials. We examine a capacitor with ferroelectric material, hysteresis by using the model evaluation mode, and a MOSFET with a gate stack using a ferroelectric material.
FinFET iN14 Calibration - Application Example
Demonstrates the usage of GTS Nano Device Simulator (NDS) to predict the short channel performance of n/pFinFETs by using calibrated scattering parameters.
FinFET iN14 Calibration - Application Example
Demonstrates the usage of GTS Nano Device Simulator (NDS) to predict the short channel performance of n/pFinFETs by using calibrated scattering parameters.
FinFET iN14 Calibration - Application Example
Demonstrates the usage of GTS Nano Device Simulator (NDS) to predict the short channel performance of n/pFinFETs by using calibrated scattering parameters.
GaN HEMT - Application Example
Demonstrates the simulation of GaN devices on the example of a HEMT.
GaN HEMT - Application Example
Demonstrates the simulation of GaN devices on the example of a HEMT.
GaN HEMT - Application Example
Demonstrates the simulation of GaN devices on the example of a HEMT.
GaN HEMT - Application Example
Demonstrates the simulation of GaN devices on the example of a HEMT.
GTS Nano Device Simulator Bulk FinFET - Application Example
Modeling n-type and p-type bulk FinFETs using GTS Nano Device Simulator (NDS). Different methods of solving the Boltzmann transport equation (BTE) and several ways to reduce the computational effort without loss of physical accuracy are used.
GTS Nano Device Simulator Bulk FinFET - Application Example
Modeling n-type and p-type bulk FinFETs using GTS Nano Device Simulator (NDS). Different methods of solving the Boltzmann transport equation (BTE) and several ways to reduce the computational effort without loss of physical accuracy are used.
GTS Nano Device Simulator Bulk FinFET - Application Example
Modeling n-type and p-type bulk FinFETs using GTS Nano Device Simulator (NDS). Different methods of solving the Boltzmann transport equation (BTE) and several ways to reduce the computational effort without loss of physical accuracy are used.
GTS Nano Device Simulator Gate-All-Around FinFET - Application Example
Modeling nMOS gate-all-around (GAA) FinFET transistors using GTS Nano Device Simulator (NDS). The impact of gate length, channel orientation and mechanical stress is investigated.
GTS Nano Device Simulator Gate-All-Around FinFET - Application Example
Modeling nMOS gate-all-around (GAA) FinFET transistors using GTS Nano Device Simulator (NDS). The impact of gate length, channel orientation and mechanical stress is investigated.
GTS Nano Device Simulator Gate-All-Around FinFET - Application Example
Modeling nMOS gate-all-around (GAA) FinFET transistors using GTS Nano Device Simulator (NDS). The impact of gate length, channel orientation and mechanical stress is investigated.
GTS Nano Device Simulator Source-Drain Tunneling - Application Example
Demonstrates the usage of the GTS Nano Device Simulator (NDS) to model the effect of source-drain tunneling in a Si nMOS and a SiGe pMOS nanowire transistor.
GTS Nano Device Simulator Source-Drain Tunneling - Application Example
Demonstrates the usage of the GTS Nano Device Simulator (NDS) to model the effect of source-drain tunneling in a Si nMOS and a SiGe pMOS nanowire transistor.
GTS Nano Device Simulator Source-Drain Tunneling - Application Example
Demonstrates the usage of the GTS Nano Device Simulator (NDS) to model the effect of source-drain tunneling in a Si nMOS and a SiGe pMOS nanowire transistor.
High-Voltage LDMOS - Tutorial
We study an LDMOS transistor using different models and simulation modes. The influence of geometric variations on the output characteristics is surveyed using GTS Structure device templates and the concept of ToolFolders. By applying impact-ionization and self-heating models, the device physics is further investigated. Finally, a transient simulation of the LDMOS switch-on behavior is performed.
High-Voltage LDMOS - Tutorial
We study an LDMOS transistor using different models and simulation modes. The influence of geometric variations on the output characteristics is surveyed using GTS Structure device templates and the concept of ToolFolders. By applying impact-ionization and self-heating models, the device physics is further investigated. Finally, a transient simulation of the LDMOS switch-on behavior is performed.
Image Sensor - Application Example
In this example, a 3D structure of 4T CMOS image sensor with variation of technology parameters is presented.
Image Sensor - Application Example
In this example, a 3D structure of 4T CMOS image sensor with variation of technology parameters is presented.
Image Sensor - Application Example
In this example, a 3D structure of 4T CMOS image sensor with variation of technology parameters is presented.
Import 3rd Party file for a GTS Minimos-NT simulation - Application Example
This example demonstrates how to import a 3rdParty device file. In a second step, the imported device is then used to set up a GTS Minimos-NT simulation.
Import 3rd Party file for a GTS Minimos-NT simulation - Application Example
This example demonstrates how to import a 3rdParty device file. In a second step, the imported device is then used to set up a GTS Minimos-NT simulation.
Import 3rd Party file for a GTS Minimos-NT simulation - Application Example
This example demonstrates how to import a 3rdParty device file. In a second step, the imported device is then used to set up a GTS Minimos-NT simulation.
Import 3rd Party file for a GTS Minimos-NT simulation - Application Example
This example demonstrates how to import a 3rdParty device file. In a second step, the imported device is then used to set up a GTS Minimos-NT simulation.
Import 3rd Party file for a GTS Minimos-NT simulation - Application Example
This example demonstrates how to import a 3rdParty device file. In a second step, the imported device is then used to set up a GTS Minimos-NT simulation.
Introduction to Cell Designer - N7 Technology Simulation – Tutorial
This tutorial describes the basic work flow of GTS Cell Designer, from layout and technology rule-based structure generation to transient device simulation to cell parameter extraction. A good starting point for more complex work flows.
Introduction to Cell Designer - N7 Technology Simulation – Tutorial
This tutorial describes the basic work flow of GTS Cell Designer, from layout and technology rule-based structure generation to transient device simulation to cell parameter extraction. A good starting point for more complex work flows.
Introduction to Cell Designer - N7 Technology Simulation – Tutorial
This tutorial describes the basic work flow of GTS Cell Designer, from layout and technology rule-based structure generation to transient device simulation to cell parameter extraction. A good starting point for more complex work flows.
Introduction to Cell Designer - N7 Technology Simulation – Tutorial
This tutorial describes the basic work flow of GTS Cell Designer, from layout and technology rule-based structure generation to transient device simulation to cell parameter extraction. A good starting point for more complex work flows.
Irradiation Simulation - Tutorial
This tutorial illustrates simulation of a single-event response due to heavy ion strikes on device structures and circuits of increasing complexity. Starting with a simple 2D MOSFET example, the influence of the ion impact position is shown. Furthermore, investigations on circuit level are carried out including a 6T-SRAM cell SEU. Finally, the 3D irradiation simulation capabilities are demonstrated.
Irradiation Simulation - Tutorial
This tutorial illustrates simulation of a single-event response due to heavy ion strikes on device structures and circuits of increasing complexity. Starting with a simple 2D MOSFET example, the influence of the ion impact position is shown. Furthermore, investigations on circuit level are carried out including a 6T-SRAM cell SEU. Finally, the 3D irradiation simulation capabilities are demonstrated.
Irradiation Simulation - Tutorial
This tutorial illustrates simulation of a single-event response due to heavy ion strikes on device structures and circuits of increasing complexity. Starting with a simple 2D MOSFET example, the influence of the ion impact position is shown. Furthermore, investigations on circuit level are carried out including a 6T-SRAM cell SEU. Finally, the 3D irradiation simulation capabilities are demonstrated.
ISPP of SONOS Devices - Application Example
The ISPP response of SONOS devices with SRH defects in the charge trapping layer is simulated using Minimos-NT. The temperature dependences of different dominant discharging mechanisms are explored.
ISPP of SONOS Devices - Application Example
The ISPP response of SONOS devices with SRH defects in the charge trapping layer is simulated using Minimos-NT. The temperature dependences of different dominant discharging mechanisms are explored.
ISPP of SONOS Devices - Application Example
The ISPP response of SONOS devices with SRH defects in the charge trapping layer is simulated using Minimos-NT. The temperature dependences of different dominant discharging mechanisms are explored.
ISPP of VNAND Devices (2.5D) - Application Example
The ISPP response of SONOS devices with SRH defects in the charge trapping layer is simulated using Minimos-NT. The temperature dependences of different dominant discharging mechanisms are explored.
ISPP of VNAND Devices (2.5D) - Application Example
The ISPP response of SONOS devices with SRH defects in the charge trapping layer is simulated using Minimos-NT. The temperature dependences of different dominant discharging mechanisms are explored.
ISPP of VNAND Devices (2.5D) - Application Example
The ISPP response of SONOS devices with SRH defects in the charge trapping layer is simulated using Minimos-NT. The temperature dependences of different dominant discharging mechanisms are explored.
kp and Low-Field Simulations - Tutorial
This tutorial demonstrates a typical work-flow for calculating the subband structure of a channel cross-section and the channel's mobility. In the first example, we will look at a nanowire, which represents a one-dimensional system of carriers. In the second example, we will recap using a MOS structure, which is a two-dimensional system.
kp and Low-Field Simulations - Tutorial
This tutorial demonstrates a typical work-flow for calculating the subband structure of a channel cross-section and the channel's mobility. In the first example, we will look at a nanowire, which represents a one-dimensional system of carriers. In the second example, we will recap using a MOS structure, which is a two-dimensional system.
kp and Low-Field Simulations - Tutorial
This tutorial demonstrates a typical work-flow for calculating the subband structure of a channel cross-section and the channel's mobility. In the first example, we will look at a nanowire, which represents a one-dimensional system of carriers. In the second example, we will recap using a MOS structure, which is a two-dimensional system.
Logic Cell Simulation with GTS Cell Designer - N7 Inverter Cell - Tutorial
This tutorial introduces the user into the work flow of GTS Cell Designer. It is a guide from layout and technology rule-based structure generation to transient device simulation to cell parameter extraction. The knowledge presented here can act as a basis for more complex design-technology co-optimization (DTCO) work flows.
Logic Cell Simulation with GTS Cell Designer - N7 Inverter Cell - Tutorial
This tutorial introduces the user into the work flow of GTS Cell Designer. It is a guide from layout and technology rule-based structure generation to transient device simulation to cell parameter extraction. The knowledge presented here can act as a basis for more complex design-technology co-optimization (DTCO) work flows.
Logic Cell Simulation with GTS Cell Designer - N7 Inverter Cell - Tutorial
This tutorial introduces the user into the work flow of GTS Cell Designer. It is a guide from layout and technology rule-based structure generation to transient device simulation to cell parameter extraction. The knowledge presented here can act as a basis for more complex design-technology co-optimization (DTCO) work flows.
Mechanical Stress Simulation - Application Example
The effects of mechanical stress in a PMOS FinFET with SiGe Source/Drain Epi layers are investigated.
Mechanical Stress Simulation - Application Example
The effects of mechanical stress in a PMOS FinFET with SiGe Source/Drain Epi layers are investigated.
Mechanical Stress Simulation - Application Example
The effects of mechanical stress in a PMOS FinFET with SiGe Source/Drain Epi layers are investigated.
Mechanical Stress Simulation - Application Example
The effects of mechanical stress in a PMOS FinFET with SiGe Source/Drain Epi layers are investigated.
Mixed-Mode Part I - Tutorial
Basic mixed-mode simulation capabilities of Minimos-NT are presented. Distributed and compact devices are used to simulate the output voltage of a single transistor inverter and a CMOS inverter. As a follow-up, we recommend to continue with the Mixed-Mode II tutorial, covering transient analysis of a COMS inverter and an entire SRAM cell.
Mixed-Mode Part I - Tutorial
Basic mixed-mode simulation capabilities of Minimos-NT are presented. Distributed and compact devices are used to simulate the output voltage of a single transistor inverter and a CMOS inverter. As a follow-up, we recommend to continue with the Mixed-Mode II tutorial, covering transient analysis of a COMS inverter and an entire SRAM cell.
Mixed-Mode Part I - Tutorial
Basic mixed-mode simulation capabilities of Minimos-NT are presented. Distributed and compact devices are used to simulate the output voltage of a single transistor inverter and a CMOS inverter. As a follow-up, we recommend to continue with the Mixed-Mode II tutorial, covering transient analysis of a COMS inverter and an entire SRAM cell.
Mixed-Mode Part II - Tutorial
This is a follow-up to the Mixed-Mode I tutorial. It shows the advanced mixed-mode simulation capabilities of Minimos-NT. First, we simulate the output characteristics of a simple CMOS inverter. Then, we extend this circuit to simulate the transient behaviour of a CMOS inverter chain and finally a whole SRAM cell.
Mixed-Mode Part II - Tutorial
This is a follow-up to the Mixed-Mode I tutorial. It shows the advanced mixed-mode simulation capabilities of Minimos-NT. First, we simulate the output characteristics of a simple CMOS inverter. Then, we extend this circuit to simulate the transient behaviour of a CMOS inverter chain and finally a whole SRAM cell.
Mixed-Mode Part II - Tutorial
This is a follow-up to the Mixed-Mode I tutorial. It shows the advanced mixed-mode simulation capabilities of Minimos-NT. First, we simulate the output characteristics of a simple CMOS inverter. Then, we extend this circuit to simulate the transient behaviour of a CMOS inverter chain and finally a whole SRAM cell.
Modeling of Interface Traps in Nano-scaled Devices - Application Example
Demonstrates the usage of the GTS Nano Device Simulator (NDS) to model a 3D nanowire FET with interface charges.
Modeling of Interface Traps in Nano-scaled Devices - Application Example
Demonstrates the usage of the GTS Nano Device Simulator (NDS) to model a 3D nanowire FET with interface charges.
Modeling of Interface Traps in Nano-scaled Devices - Application Example
Demonstrates the usage of the GTS Nano Device Simulator (NDS) to model a 3D nanowire FET with interface charges.
Modeling of Interface Traps in Nano-scaled Devices - Application Example
Demonstrates the usage of the GTS Nano Device Simulator (NDS) to model a 3D nanowire FET with interface charges.
MoS2 MOSFET Simulation Schottky Barrier Tunneling - Application Example
Example that shows how the electrostatics can affect the conductivity of two dimensional semiconductors as well as their Schottky barriers with bulk metal contacts.
MoS2 MOSFET Simulation Schottky Barrier Tunneling - Application Example
Example that shows how the electrostatics can affect the conductivity of two dimensional semiconductors as well as their Schottky barriers with bulk metal contacts.
MoS2 MOSFET Simulation Schottky Barrier Tunneling - Application Example
Example that shows how the electrostatics can affect the conductivity of two dimensional semiconductors as well as their Schottky barriers with bulk metal contacts.
NDS FinFET N7 - Application Example
NDS simulations with N7 like n/pFinFET for simulating IdVg curves.
NDS FinFET N7 - Application Example
NDS simulations with N7 like n/pFinFET for simulating IdVg curves.
NDS FinFET N7 - Application Example
NDS simulations with N7 like n/pFinFET for simulating IdVg curves.
NDS NS N3 - Application Example
NDS simulations with n/pNST (Nano-sheet transistor) for N3 generation and beyond.
NDS NS N3 - Application Example
NDS simulations with n/pNST (Nano-sheet transistor) for N3 generation and beyond.
NDS NS N3 - Application Example
NDS simulations with n/pNST (Nano-sheet transistor) for N3 generation and beyond.
NDS NS N3 LSG - Application Example
NDS simulations with a NST (Nano-sheet transistor) from Layout tool folder.
NDS NS N3 LSG - Application Example
NDS simulations with a NST (Nano-sheet transistor) from Layout tool folder.
NDS NS N3 LSG - Application Example
NDS simulations with a NST (Nano-sheet transistor) from Layout tool folder.
NDS NS N3 LSG - Application Example
NDS simulations with a NST (Nano-sheet transistor) from Layout tool folder.
NDS Simulation on an Imported 3rd Party File - Application Example
Setup an NDS simulation on an imported 3rd party device file.
NDS Simulation on an Imported 3rd Party File - Application Example
Setup an NDS simulation on an imported 3rd party device file.
NDS Simulation on an Imported 3rd Party File - Application Example
Setup an NDS simulation on an imported 3rd party device file.
NDS Simulation on an Imported 3rd Party File - Application Example
Setup an NDS simulation on an imported 3rd party device file.
NDS Simulation on an Imported 3rd Party File - Application Example
Setup an NDS simulation on an imported 3rd party device file.
NMOS at cryogenic temperatures using QFT - Application Example
Use of Quasi Fermi Transport model to simulate planar technology transistors at cryogenic temperatures.
NMOS at cryogenic temperatures using QFT - Application Example
Use of Quasi Fermi Transport model to simulate planar technology transistors at cryogenic temperatures.
NMOS at cryogenic temperatures using QFT - Application Example
Use of Quasi Fermi Transport model to simulate planar technology transistors at cryogenic temperatures.
Parasitics Extraction of an Inverter Cell - Application Example
Demonstrates the extraction of parasitic resistances and capacitances (PEX) on the example of an inverter cell in FinFET technology. Processing, visualization of data and extraction of netlists are shown.
Parasitics Extraction of an Inverter Cell - Application Example
Demonstrates the extraction of parasitic resistances and capacitances (PEX) on the example of an inverter cell in FinFET technology. Processing, visualization of data and extraction of netlists are shown.
Parasitics Extraction of an Inverter Cell - Application Example
Demonstrates the extraction of parasitic resistances and capacitances (PEX) on the example of an inverter cell in FinFET technology. Processing, visualization of data and extraction of netlists are shown.
Path-finding for Future Technologies - Application Example
Demonstrates the usage of GTS Nano Device Simulator (NDS) to investigate the performance of a scaled-down bulk nFinFET.
Path-finding for Future Technologies - Application Example
Demonstrates the usage of GTS Nano Device Simulator (NDS) to investigate the performance of a scaled-down bulk nFinFET.
Path-finding for Future Technologies - Application Example
Demonstrates the usage of GTS Nano Device Simulator (NDS) to investigate the performance of a scaled-down bulk nFinFET.
Perturbation-Mode Variability Calculation for N7 FinFET - Application Example
This is a template for creating a new application example. Please write a nice, concise and complete abstract which includes all important aspects and keywords!
Perturbation-Mode Variability Calculation for N7 FinFET - Application Example
This is a template for creating a new application example. Please write a nice, concise and complete abstract which includes all important aspects and keywords!
Perturbation-Mode Variability Calculation for N7 FinFET - Application Example
This is a template for creating a new application example. Please write a nice, concise and complete abstract which includes all important aspects and keywords!
Perturbation-Mode Variability Calculation for N7 FinFET - Application Example
This is a template for creating a new application example. Please write a nice, concise and complete abstract which includes all important aspects and keywords!
Polycrystalline Ferroelectric Transistors - Application Example
A series of studies on a ferroelectric capacitor designed to introduce the Kinetic Monte Carlo (KMC) based ferroelectric models available within the GTS Framework
Polycrystalline Ferroelectric Transistors - Application Example
A series of studies on a ferroelectric capacitor designed to introduce the Kinetic Monte Carlo (KMC) based ferroelectric models available within the GTS Framework
Polycrystalline Ferroelectric Transistors - Application Example
A series of studies on a ferroelectric capacitor designed to introduce the Kinetic Monte Carlo (KMC) based ferroelectric models available within the GTS Framework
Polycrystalline Ferroelectric Transistors - Application Example
A series of studies on a ferroelectric capacitor designed to introduce the Kinetic Monte Carlo (KMC) based ferroelectric models available within the GTS Framework
Projects, ToolFolders, Device Simulation - Getting Started I Tutorial
The general handling of GTS Framework is introduced by rather basic examples. The basic uses of GTS Structure and Minimos-NT are illustrated as well as the concept of ToolFolders and the related workflow functions. Recommended to get a first impression!
Projects, ToolFolders, Device Simulation - Getting Started I Tutorial
The general handling of GTS Framework is introduced by rather basic examples. The basic uses of GTS Structure and Minimos-NT are illustrated as well as the concept of ToolFolders and the related workflow functions. Recommended to get a first impression!
Projects, ToolFolders, Device Simulation - Getting Started I Tutorial
The general handling of GTS Framework is introduced by rather basic examples. The basic uses of GTS Structure and Minimos-NT are illustrated as well as the concept of ToolFolders and the related workflow functions. Recommended to get a first impression!
Projects, ToolFolders, Device Simulation - Getting Started I Tutorial
The general handling of GTS Framework is introduced by rather basic examples. The basic uses of GTS Structure and Minimos-NT are illustrated as well as the concept of ToolFolders and the related workflow functions. Recommended to get a first impression!
Projects, ToolFolders, Device Simulation - Getting Started I Tutorial
The general handling of GTS Framework is introduced by rather basic examples. The basic uses of GTS Structure and Minimos-NT are illustrated as well as the concept of ToolFolders and the related workflow functions. Recommended to get a first impression!
Reliability Post Minimos BTI - Application Example
In this example, the compact-physics simulator Comphy is integrated in a TCAD flow to simulate the reliability of FETs. The full accuracy of 3D TCAD is maintained for the efficient calculations of the transient charging and discharging of the defects in the oxides and at the interfaces.
Reliability Post Minimos BTI - Application Example
In this example, the compact-physics simulator Comphy is integrated in a TCAD flow to simulate the reliability of FETs. The full accuracy of 3D TCAD is maintained for the efficient calculations of the transient charging and discharging of the defects in the oxides and at the interfaces.
Reliability Post Minimos BTI - Application Example
In this example, the compact-physics simulator Comphy is integrated in a TCAD flow to simulate the reliability of FETs. The full accuracy of 3D TCAD is maintained for the efficient calculations of the transient charging and discharging of the defects in the oxides and at the interfaces.
Reliability Post Minimos BTI - Application Example
In this example, the compact-physics simulator Comphy is integrated in a TCAD flow to simulate the reliability of FETs. The full accuracy of 3D TCAD is maintained for the efficient calculations of the transient charging and discharging of the defects in the oxides and at the interfaces.
Reliability Post Minimos BTI - Application Example
In this example, the compact-physics simulator Comphy is integrated in a TCAD flow to simulate the reliability of FETs. The full accuracy of 3D TCAD is maintained for the efficient calculations of the transient charging and discharging of the defects in the oxides and at the interfaces.
Retention of SONOS Devices - Application Example
The retention behavior of SONOS devices with SRH defects in the charge trapping layer is simulated using Minimos-NT. The temperature dependences of different dominant discharging mechanisms are explored.
Retention of SONOS Devices - Application Example
The retention behavior of SONOS devices with SRH defects in the charge trapping layer is simulated using Minimos-NT. The temperature dependences of different dominant discharging mechanisms are explored.
Retention of SONOS Devices - Application Example
The retention behavior of SONOS devices with SRH defects in the charge trapping layer is simulated using Minimos-NT. The temperature dependences of different dominant discharging mechanisms are explored.
Schottky Barrier Diode - Application Example
Demonstrates the simulation of SiC devices on the example of Schottky Barrier Diode (SBD). Temperature dependence as well as breakdown curve with breakthrough/snapback effect were simulated in Minimos-NT.
Schottky Barrier Diode - Application Example
Demonstrates the simulation of SiC devices on the example of Schottky Barrier Diode (SBD). Temperature dependence as well as breakdown curve with breakthrough/snapback effect were simulated in Minimos-NT.
Schottky Barrier Diode - Application Example
Demonstrates the simulation of SiC devices on the example of Schottky Barrier Diode (SBD). Temperature dependence as well as breakdown curve with breakthrough/snapback effect were simulated in Minimos-NT.
Schrödinger-Poisson Simulation - Tutorial
This tutorial demonstrates a basic work-flow for analyzing FinFET or nanowire cross-sections using VSP. Parameterized nanowire templates for rectangular as well as triangular and circular cross-sections are awailable in GTS Structure. A self-consistent solution of the effective mass closed boundary Schroedinger carrier model and the Poisson equation are calculated for (100) and (110) substrate orientation. The wavefunctions are exported to a text file.
Schrödinger-Poisson Simulation - Tutorial
This tutorial demonstrates a basic work-flow for analyzing FinFET or nanowire cross-sections using VSP. Parameterized nanowire templates for rectangular as well as triangular and circular cross-sections are awailable in GTS Structure. A self-consistent solution of the effective mass closed boundary Schroedinger carrier model and the Poisson equation are calculated for (100) and (110) substrate orientation. The wavefunctions are exported to a text file.
Schrödinger-Poisson Simulation - Tutorial
This tutorial demonstrates a basic work-flow for analyzing FinFET or nanowire cross-sections using VSP. Parameterized nanowire templates for rectangular as well as triangular and circular cross-sections are awailable in GTS Structure. A self-consistent solution of the effective mass closed boundary Schroedinger carrier model and the Poisson equation are calculated for (100) and (110) substrate orientation. The wavefunctions are exported to a text file.
Schrödinger-Poisson Simulation - Tutorial
This tutorial demonstrates a basic work-flow for analyzing FinFET or nanowire cross-sections using VSP. Parameterized nanowire templates for rectangular as well as triangular and circular cross-sections are awailable in GTS Structure. A self-consistent solution of the effective mass closed boundary Schroedinger carrier model and the Poisson equation are calculated for (100) and (110) substrate orientation. The wavefunctions are exported to a text file.
Self-Heating Simulation of Inverter Cells - Application Example
Demonstrates the usage of GTS Minimos-NT and Cell Designer to investigate self heating of FinFET inverter cells.
Self-Heating Simulation of Inverter Cells - Application Example
Demonstrates the usage of GTS Minimos-NT and Cell Designer to investigate self heating of FinFET inverter cells.
Self-Heating Simulation of Inverter Cells - Application Example
Demonstrates the usage of GTS Minimos-NT and Cell Designer to investigate self heating of FinFET inverter cells.
Self-Heating Simulation of Inverter Cells - Application Example
Demonstrates the usage of GTS Minimos-NT and Cell Designer to investigate self heating of FinFET inverter cells.
Series Resistance Extraction - Application Example
The usage of Series Resistance Extraction Python Toolfolder for various NMOS devices is shown.
Series Resistance Extraction - Application Example
The usage of Series Resistance Extraction Python Toolfolder for various NMOS devices is shown.
Series Resistance Extraction - Application Example
The usage of Series Resistance Extraction Python Toolfolder for various NMOS devices is shown.
Series Resistance Extraction - Application Example
The usage of Series Resistance Extraction Python Toolfolder for various NMOS devices is shown.
SiC diode using QFT - Application Example
Use of Quasi Fermi Transport model to simulate SiC diodes in strong reverse bias.
SiC diode using QFT - Application Example
Use of Quasi Fermi Transport model to simulate SiC diodes in strong reverse bias.
SiC diode using QFT - Application Example
Use of Quasi Fermi Transport model to simulate SiC diodes in strong reverse bias.
SiC MESFET - Application Example
Demonstrates the simulation of SiC devices on the example of a power MESFET.
SiC MESFET - Application Example
Demonstrates the simulation of SiC devices on the example of a power MESFET.
SiC MESFET - Application Example
Demonstrates the simulation of SiC devices on the example of a power MESFET.
SiC Vertical DMOS - Application Example
Demonstrates the simulation of SiC devices on the example of a vertical DMOS (VDMOS). The switch from voltage to current stepping is utilized for the simulation of the breakdown curve.
SiC Vertical DMOS - Application Example
Demonstrates the simulation of SiC devices on the example of a vertical DMOS (VDMOS). The switch from voltage to current stepping is utilized for the simulation of the breakdown curve.
SiC Vertical DMOS - Application Example
Demonstrates the simulation of SiC devices on the example of a vertical DMOS (VDMOS). The switch from voltage to current stepping is utilized for the simulation of the breakdown curve.
Simulation Flow with DOE, Process and Device Splits - Getting Started II Tutorial
We demonstrate the Design of Experiment (DOE) feature of GTS Framework. A workflow with structure generation, device simulation and parameter extraction is shown, including off-current normalization.
Simulation Flow with DOE, Process and Device Splits - Getting Started II Tutorial
We demonstrate the Design of Experiment (DOE) feature of GTS Framework. A workflow with structure generation, device simulation and parameter extraction is shown, including off-current normalization.
Simulation Flow with DOE, Process and Device Splits - Getting Started II Tutorial
We demonstrate the Design of Experiment (DOE) feature of GTS Framework. A workflow with structure generation, device simulation and parameter extraction is shown, including off-current normalization.
Simulation Flow with DOE, Process and Device Splits - Getting Started II Tutorial
We demonstrate the Design of Experiment (DOE) feature of GTS Framework. A workflow with structure generation, device simulation and parameter extraction is shown, including off-current normalization.
Simulation Flow with DOE, Process and Device Splits - Getting Started II Tutorial
We demonstrate the Design of Experiment (DOE) feature of GTS Framework. A workflow with structure generation, device simulation and parameter extraction is shown, including off-current normalization.
SOI FinFET - Application Example
Demonstrates a basic simulation flow on the basis of an SOI FinFET. Drift Diffusion and Density Gradient simulations of IV, CV curves and Gate leakage analysis have been performed.
SOI FinFET - Application Example
Demonstrates a basic simulation flow on the basis of an SOI FinFET. Drift Diffusion and Density Gradient simulations of IV, CV curves and Gate leakage analysis have been performed.
SOI FinFET Discrete Traps and Dopants - Application Example
Based on a FinFET structure, the influence of discrete interface and oxide traps as well as discrete dopants on the device characteristics are simulated in Minimos-NT.
SOI FinFET Discrete Traps and Dopants - Application Example
Based on a FinFET structure, the influence of discrete interface and oxide traps as well as discrete dopants on the device characteristics are simulated in Minimos-NT.
SOI FinFET Discrete Traps and Dopants - Application Example
Based on a FinFET structure, the influence of discrete interface and oxide traps as well as discrete dopants on the device characteristics are simulated in Minimos-NT.
Transconductance Variability in VNAND Devices - Application Example
Simulation of 3D VNAND structures with grains in the silicon channel. We demonstrate computing the transconductance of such devices with deterministic placement of grains, randomly distributed grains, and orientation-dependent mobilities of the grains.
Transconductance Variability in VNAND Devices - Application Example
Simulation of 3D VNAND structures with grains in the silicon channel. We demonstrate computing the transconductance of such devices with deterministic placement of grains, randomly distributed grains, and orientation-dependent mobilities of the grains.
Transconductance Variability in VNAND Devices - Application Example
Simulation of 3D VNAND structures with grains in the silicon channel. We demonstrate computing the transconductance of such devices with deterministic placement of grains, randomly distributed grains, and orientation-dependent mobilities of the grains.
Variability Simulation - Tutorial
Demonstrates calculation of the fluctuations in electrical characteristic due to random discrete dopants (RDD) and metal grain roughness (MGR).
Variability Simulation - Tutorial
Demonstrates calculation of the fluctuations in electrical characteristic due to random discrete dopants (RDD) and metal grain roughness (MGR).
Variability Simulation - Tutorial
Demonstrates calculation of the fluctuations in electrical characteristic due to random discrete dopants (RDD) and metal grain roughness (MGR).
VSP – Effect of Interface Traps on Mobility - Application Example
Demonstrates the usage of VSP to calculate the effect of charged interface traps on the mobility of an nMOSCap and an nFinFET for a range of interface trap densities.
VSP – Effect of Interface Traps on Mobility - Application Example
Demonstrates the usage of VSP to calculate the effect of charged interface traps on the mobility of an nMOSCap and an nFinFET for a range of interface trap densities.
VSP – Effect of Interface Traps on Mobility - Application Example
Demonstrates the usage of VSP to calculate the effect of charged interface traps on the mobility of an nMOSCap and an nFinFET for a range of interface trap densities.
VSP – Effect of Interface Traps on Mobility - Application Example
Demonstrates the usage of VSP to calculate the effect of charged interface traps on the mobility of an nMOSCap and an nFinFET for a range of interface trap densities.
VSP Bulk Band Structure - Application Example
Demonstrates the VSP simulation of Si bulk band structure by kp model of different crystal orientations and applied stresses.
VSP Bulk Band Structure - Application Example
Demonstrates the VSP simulation of Si bulk band structure by kp model of different crystal orientations and applied stresses.
VSP Bulk Band Structure - Application Example
Demonstrates the VSP simulation of Si bulk band structure by kp model of different crystal orientations and applied stresses.
VSP Bulk Band Structure - Application Example
Demonstrates the VSP simulation of Si bulk band structure by kp model of different crystal orientations and applied stresses.
VSP Double-Gate nMOS Capacitance - Application Example
Demonstrates the usage of GTS tools to setup an nDGMOS calculating the sub-band structure and charge density for different orientations and stresses.
VSP Double-Gate nMOS Capacitance - Application Example
Demonstrates the usage of GTS tools to setup an nDGMOS calculating the sub-band structure and charge density for different orientations and stresses.
VSP Double-Gate nMOS Capacitance - Application Example
Demonstrates the usage of GTS tools to setup an nDGMOS calculating the sub-band structure and charge density for different orientations and stresses.
VSP FinFET N7 Mobility - Application Example
Demonstrates a basic simulation flow on the basis of FinFET structure. Charge density and low field mobility of Si channel are calculated using VSP.
VSP FinFET N7 Mobility - Application Example
Demonstrates a basic simulation flow on the basis of FinFET structure. Charge density and low field mobility of Si channel are calculated using VSP.
VSP FinFET N7 Mobility - Application Example
Demonstrates a basic simulation flow on the basis of FinFET structure. Charge density and low field mobility of Si channel are calculated using VSP.
VSP FinFET nMOS - Application Example
Demonstrates the usage of GTS tools to setup a FinFET nMOS calculating the sub-band structure and charge density for different orientations and stresses.
VSP FinFET nMOS - Application Example
Demonstrates the usage of GTS tools to setup a FinFET nMOS calculating the sub-band structure and charge density for different orientations and stresses.
VSP FinFET nMOS - Application Example
Demonstrates the usage of GTS tools to setup a FinFET nMOS calculating the sub-band structure and charge density for different orientations and stresses.
VSP GAA nMOS - Application Example
Demonstrates the usage of GTS tools to setup a GAA nMOS (particulary nanowire and nanosheet structures) calculating the sub-band structure and charge density for different orientations and stresses.
VSP GAA nMOS - Application Example
Demonstrates the usage of GTS tools to setup a GAA nMOS (particulary nanowire and nanosheet structures) calculating the sub-band structure and charge density for different orientations and stresses.
VSP GAA nMOS - Application Example
Demonstrates the usage of GTS tools to setup a GAA nMOS (particulary nanowire and nanosheet structures) calculating the sub-band structure and charge density for different orientations and stresses.
VSP NS N3 Mobility - Application Example
Demonstrates a basic simulation flow on the basis of nanosheet structure. Charge density and low field mobility of Si channel are calculated using VSP.
VSP NS N3 Mobility - Application Example
Demonstrates a basic simulation flow on the basis of nanosheet structure. Charge density and low field mobility of Si channel are calculated using VSP.
VSP NS N3 Mobility - Application Example
Demonstrates a basic simulation flow on the basis of nanosheet structure. Charge density and low field mobility of Si channel are calculated using VSP.
VSP Planar nMOS Capacitance - Application Example
Demonstrates the usage of GTS tools to setup a Planar nMOSCAP calculating the sub-band structure and charge density for different orientations and stresses.
VSP Planar nMOS Capacitance - Application Example
Demonstrates the usage of GTS tools to setup a Planar nMOSCAP calculating the sub-band structure and charge density for different orientations and stresses.
VSP Planar nMOS Capacitance - Application Example
Demonstrates the usage of GTS tools to setup a Planar nMOSCAP calculating the sub-band structure and charge density for different orientations and stresses.
VSP Planar Universal Mobility Curves - Application Example
The universal mobility curves of different Si surface orientations are calibrated, with a new position-dependent Dac model included in this work.
VSP Planar Universal Mobility Curves - Application Example
The universal mobility curves of different Si surface orientations are calibrated, with a new position-dependent Dac model included in this work.
VSP Planar Universal Mobility Curves - Application Example
The universal mobility curves of different Si surface orientations are calibrated, with a new position-dependent Dac model included in this work.
VSP simulation on cuts of an imported 3rd Party file - Application Example
Set up a VSP simulation on a 1D and/or 2D cut through an imported 3rd party device file
VSP simulation on cuts of an imported 3rd Party file - Application Example
Set up a VSP simulation on a 1D and/or 2D cut through an imported 3rd party device file
VSP simulation on cuts of an imported 3rd Party file - Application Example
Set up a VSP simulation on a 1D and/or 2D cut through an imported 3rd party device file
VSP simulation on cuts of an imported 3rd Party file - Application Example
Set up a VSP simulation on a 1D and/or 2D cut through an imported 3rd party device file
VSP simulation on cuts of an imported 3rd Party file - Application Example
Set up a VSP simulation on a 1D and/or 2D cut through an imported 3rd party device file
Other Downloads: Publications, Whitepapers, Software & Documentation