Rapid Creation of Simulation-Ready Cells
Combining process emulators with device simulators poses difficulties, ranging from technical ones such as artifacts and large mesh sizes to organizational ones such as limited access to detailed process data. We have a much faster, yet valid alternative:
Layout-based Structure Generation
The Layout-based Structure Generation (LSG) within GTS Cell Designer creates simulation-ready full-cell structures based on layouts and technology descriptions, which allows to efficiently analyze all circuit-level implications of:
- LER in fins, gates and BEOL
- Mask misalignment
- Lithography effects
- Device-to-device correlation
- Combined FEOL / BEOL modeling
- Awareness of self-alignment techniques
The DTCO workflow that works
Using the parameters calculated by GTS Nano Device Simulator (NDS), you can simulate full cells in 3D. You can study cell and device variability, calculate parasitics, PPA, and gain insight on variability and reliability. And of course, you can run optimizations for various aspects.
Cell Designer Tutorials
Take a step-by-step introduction to see what GTS Cell Designer can do for you. There are two tutorials; a basic introduction and an application exampe showing an inverter based on N7 FinFETs:
Read more on physics-based device simulation: Hot Topic "Physical Modeling"