At the 2017 VLSI Technology Systems and Applications symposia (2017 VLSI-TSA, April 24-27) in Taiwan, GTS researchers are presenting a novel approach for extracting the power-performance-area PPA parameter and their variability directly from a TCAD model of a logic cell.
The process involves layout-based structure generation based on technology description files, transient device simulation, and parameter extraction of timing delays and power consumption. Different sources of global and local variability can be added to investigate the sensitivity of timing and power parameters. The entire process is quick and fully automated from GDSII file to PPA characteristics, and is thus suitable for use by cell designers as well as circuit designers. The extracted parameters and statistics can be directly used in high-level descriptions of digital circuits and systems.
The histogram plots show the statistical distribution of the extracted switching parameters of the NAND cell: switching time (top left), maximum power consumption while switching (top right), energy consumption during one switch from on to off state (bottom left), static power consumption (bottom right); Inputs: inA=false, inB=true.
The VLSI-TSA symposium takes place in Hsinchu, Taiwan, at April 24-27, 2017. Our poster is presented in session T1-10 on Tuesday, April 25 at Ballroom D, from 11:50 AM until 13:30 PM.
For details, please refer to the VLSI-TSA web site.