V-NAND application example: Channel trans-conductance
Modeling and simulation of V-NAND poly-silicon channel trans-conductance, including variability
Mobility reduction at grain boundaries in V-NAND device
V-NAND Transconductance Variability
Starting with release 2018.03, GTS Framework can calculate the transconductance statistics of V-NAND flash devices. Macaroni structures show a strong variability in their transconductance behavior, which is due to the formation of grains in the silicon channel during the production process.
GTS Framework allows to study the effects of:
- Average poly-grain size
- Bias conditions and device temperature
- Mobility reduction at grain boundaries
Furthermore, you can study the following variability sources:
- Random structure of grains and grain boundaries
- Discrete traps & discrete charging
- Random crystal orientations of the grains in the channel
- Random position and energy of traps along the grain boundaries
- Random position of traps in the grains
For more, have a look at our respective application example, which will be online soon.
The images above show a typical ensemble of IDVG curves (left) and typical histograms of threshold voltages Vth (center) and on currents ION (right), respectively.