GTS is strenthening its leading position in TCAD device simulation in general as well as specifically regarding FinFET technologies and ultra-scaled transistors. In four oral presentations, two in cooperation with scientists from TU Vienna, GTS developers address various topics and solutions, all based on GTS Framework:
|Thu, Sept. 10: Paper Session 10: Novel TCAD Applications|
|1:50 PM||Harald Demel||Expanding TCAD Simulations from Grid to Cloud|
|2:50 PM||Christian Kernstock||Layout-Based TCAD Device Model Generation|
|Thu, Sept. 10: Paper Session 11: Silicon Devices|
||Efficient Modeling of Source/Drain Tunneling
in Ultra-Scaled Transistors
|Fri, Sept. 11: Paper Session 13: Finfets|
|Markus Karner||Hierarchical TCAD Device Simulation of FinFETs|
H. Demel, Z. Stanojevic ́, and M. Karner (GTS)
G. Rzepa and T. Grasser (TU Vienna)
In this work, the distribution, execution and performance of TCAD simulations on grid and cloud systems are investigated. A module for distributed computing which can uniformly interface both grid and cloud computing systems has been implemented within GTS Framework. Automated allocation of resources for user jobs on a combined platform has been achieved. Traditional grid-computing systems are compared with cloud-based systems. Strategies for cost-effective allocation of cloud-resources are presented. The performance of a typical TCAD application run on a grid, in the cloud, and a hybrid system combining both is assessed.
See hot topic: Extending TCAD Simulation from Grid to Cloud
C. Kernstock, Z. Stanojevic ́, O. Baumgartner, and M. Karner
A fully automated process emulation is presented. Starting from industrial standard gdsII mask files, a user-friendly and fast way to create TCAD-ready models has been realized. A three-step approach is used. The creation of virtual layers to allow for logical operation based on masks is shown. Then, the geometrical and dopant profile instantiation is carried out. Third, the mesh generation based on and optimized on the information of the first two steps is shown. Industry-relevant sample applications for the implemented work-flow ranging from a radiation-hardened latch to a state of the art FinFET SRAM cell are demonstrated.
O. Baumgartner, M. Karner, Z. Stanojevic ́, H.W. Cheng-Karner (GTS),
La. Filipovic ́, and H. Kosina (TU Vienna)
In this work, a comprehensive investigation of the effect of source/drain tunneling in ultra-scaled transistors is presented. A novel approach to efficiently and accurately incorporate the quantum-mechanical effects of source/drain (S/D) tunneling in semi-classical device simulators has been developed. The ballistic quantum transport model has been implemented as part of the Vienna-Schrödinger-Poisson simulation and modeling framework. The transport formalism is based on the quantum transmitting boundary method and has been extended to provide recombination and generation rates of carriers due to the direct tunneling current across the source/drain barrier. The model has been used to investigate the effect of direct S/D tunneling on device performance in ultra-scaled double-gate and nanowire transistors. The variations in transfer and output characteristics due to the tunneling effect have been calculated for various gate lengths and channel widths. The influence on the drain induced barrier lowering (DIBL) is shown.
M. Karner, Z. Stanojevic ́, C. Kernstock, H.W. Cheng-Karner, O. Baumgartner
A framework for FinFET design studies is presented. Our physics-based modeling approach allows to accurately capture the effects of channel cross-section, orientation and strain as well as contact resistance – for the first time all in one tool. Using this approach as a reference, the predictiveness of empirical TCAD models is extended by re-calibration. Our hierarchical tool chain is embedded in an industry-proven framework equipped with DOE and optimization modules. The capabilities are demonstrated in a simulation study on a recent FinFET technology node.
The International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) 2015 takes place in Washington, DC, USA, September 9-11, 2015.
For details and program, please visit the SISPAD web site.