Trap response analysis in GTS Framework was used in paper 32.1 by Devin Verreck et al. ("Quantitative 3-D Model to Explain Large Single Trap Charge Variability in Vertical NAND Memory"). Join the session, and learn more at the GTS booth in the exhibits area! CEO Markus Karner and Senior Scientist Franz Schanovsky will be happy to show you our latest products and concepts for physical device simulation, cell simulation including parasitics, reliability, variability, DTCO and the related workflows.
If this is your topic, be sure to check session 21 Emerging Transistor Reliability and Pertinent Strategies, co-chaired by Franz Schanovsky (Senior Scientist at GTS). Read more in our News area.
December 7-11, 2019
Hilton San Francisco Union Square
333 O’Farrell Street
San Francisco, CA 94102
Monday: 12pm – 4:00pm
Tuesday: 8:00am – 4:00pm
Wednesday: 8:00am – 12:00pm