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Identifying Crucial Aspects for Stacked NW FET - IEDM 2016

In their 2016 IEDM paper, GTS scientists present latest results with direct implications on upcoming nanowire technologies.

Idealized stacked NW-FET; electron concentration at VG = Vth, VDS =0.9V

The paper Vertically Stacked Nanowire MOSFETS for Sub-10 nm Nodes: Advanced Topography, Device, Variability, and Reliability Simulations points out several critical aspects that need to be addressed for the technology to surpass current FinFETs. The results include:

  1. New parasitic capacitances are introduced by the fabrication process
  2. Degradation of the on-current due to impurities in the gate stack
  3. Device time-zero variability increases due to a lower amount of dopant atoms per device
  4. The device is more affected by BTI than a comparable FinFET

Predictively providing such substantial data, the used physical models reveal insight on problems to expect and how they can be tackled. They allow thorough DTCO, and provide profound data to make the right decisions in Path-Finding.

Read more on our IEDM 2016 page.