Global TCAD Solutions

Cutting-Edge TCAD

IEDM 2016 – Join us in San Francisco!

Nanowire vs. FinFET - topology device, variability, reliability

Building upon Physical Modeling as published in our IEDM 2015 paper, this year's IEDM paper describes advanced topography, device, variability, and reliability simulations of nanowire MOSFETs.

But this is not all – we are cordially inviting you to our two IEDM Exhibitor Events, all taking place within IEEE IEDM 2016 at the Hilton San Francisco Union Square:

Sun 7:00pm: From Physics to Circuit

Simulation of logic cells: Talk, discussion, wine and beer
Sunday Dec 4, 7:00 – 9:00 pm, Union Square 5-6 — more below

Mon 5:00pm: GTS TCAD in the Future

New strategic perspectives
Monday Dec 5, 5:00 – 6:30 pm, Union Square 5-6 — more below

Wed 11:35am: IEDM Paper Talk 30.7

Vertically Stacked Nanowire MOSFETs for Sub-10 nm Nodes: Advanced Topography, Device, Variability, and Reliability Simulations
Wednesday Dec 7, 11:35am, Session 30.7 — more below

Mon-Wed: Exhibitor Booth 7

Visit our booth in the Exhibits area
Monday-Wednesday, Exhibits Area, Yosemite Ballroom

From Physics to Circuits: Advanced CMOS Logic & Memory

Physics-based Simulation of Logic Cells

Taking physics-based simulation one step further, GTS tools can already simulate complete circuits on device level, such as this NAND gate – but we are not satisfied yet:

GTS becoming IMEC Partner

IMEC and GTS tighten their collaboration in the field of reliability / variability of advanced CMOS logic and memory technologies by entering a Joint Development Program (JDP).

Join us on Sun Dec. 4, 7:00pm for some snacks, beer or wine to hear how you can benefit from our research activities, and see how GTS products can help you with:
Power, Performance, Area, Variability, Reliability
DTCO (Design-Technology Co-Optimization)

Please register (email) to attend this event.

GTS TCAD in the Future

Our vision is to provide solutions based on leading-edge research, which are efficient and easy to use. We put high emphasis on interoperability and integration with industry standards, to help our clients benefit from a comprehensive working environment — and we are just leveraging this aspect.

Get surprized on GTS TCAD perspectives on Mon Dec 5, 5:00pm.

Please register (email) to attend this event.

IEDM 2016 Paper Talk: Topography, Device, Reliability, Variability

Vertically Stacked Nanowire MOSFETS for Sub-10 nm Nodes

Using latest models within GTS Framework, GTS scientists analyze a recent sub-10 nm technology demonstration based on stacked nanowire transistors (NW-FETs). The study encompasses:

Right: Simulated transfer characteristics of the device compared to measurements. Left: Comparison of the PBT degradation and recovery transients of the stacked nanowire structure (red) and an equivalent FinFET structure (blue)

  1. Topography simulation which realistically reproduces the fabricated device
  2. Device simulation based on the subband Boltzmann transport equation
  3. Acomprehensive set of scattering models for the gate stack
  4. Physical models for time-zero variability and BTI device degradation.

Comparing Nanowire to FinFET

The findings reveal several critical aspects that need to be addressed for nanowire technology to surpass current FinFETs, such as:

  • New process-induced parasitic capacitances that would not be present in a comparable FinFET
  • Degradation of the on-current due to impurities in the gate stack
  • Increased device time-zero variability due to a lower amount of dopant atoms per device
  • The device is more affected by BTI than a comparable FinFET

Applications: Path-Finding, DTCO

The paper, titled Vertically Stacked Nanowire MOSFETs for Sub-10 nm Nodes: Advanced Topography, Device, Variability, and Reliability Simulations, shows how to obtain qualitative and quantitative data for tackling problems as well as for making the right decisions in Path-Finding and DTCO.


After adaption for industrial use, the developed models will be awailable within GTS Framework Nano Device Simulator.


For more information, or to schedule a meeting at IEDM, please contact us!