Vertically Stacked Nanowire MOSFETS for Sub-10 nm Nodes
Using latest models within GTS Framework, GTS scientists analyze a recent sub-10 nm technology demonstration based on stacked nanowire transistors (NW-FETs). The study encompasses:
- Topography simulation which realistically reproduces the fabricated device
- Device simulation based on the subband Boltzmann transport equation
- Acomprehensive set of scattering models for the gate stack
- Physical models for time-zero variability and BTI device degradation.
Comparing Nanowire to FinFET
The findings reveal several critical aspects that need to be addressed for nanowire technology to surpass current FinFETs, such as:
- New process-induced parasitic capacitances that would not be present in a comparable FinFET
- Degradation of the on-current due to impurities in the gate stack
- Increased device time-zero variability due to a lower amount of dopant atoms per device
- The device is more affected by BTI than a comparable FinFET
Applications: Path-Finding, DTCO
The paper, titled Vertically Stacked Nanowire MOSFETs for Sub-10 nm Nodes: Advanced Topography, Device, Variability, and Reliability Simulations, shows how to obtain qualitative and quantitative data for tackling problems as well as for making the right decisions in Path-Finding and DTCO.
After adaption for industrial use, the developed models will be awailable within GTS Framework Nano Device Simulator.
For more information, or to schedule a meeting at IEDM, please contact us!