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(We keep distortion to a minimum, not releasing more than ca. 12 items per year.)
GTS scientific team enhanced by oxide reliability modeling specialist
In the new CD Laboratory at the TU Wien, Infineon Technologies AG, ams AG and Global TCAD Solutions GmbH are working together on understanding the physics of gate oxide reliability in semiconductor devices.
Zlatan Stanojević, CTO of Global TCAD Solutions, will hold a talk on "Innovation in TCAD from a Start-Up Perspective" in the Modelling and Simulation session, at 15:15 on Dec. 18th, 2018.
Visit the GTS booth in the IEDM exhibits area and join our presentation at MOS-AK workshop on Dec 5
New applications: TCAD in DTCO, self-heating (SH) simulation for logic cells, germanium gate-all-around architectures (GAA)
GTS presenting first practical TCAD-based work flow for design-technology co-optimization (DTCO) of standard cells.
Next to its contribution at VLSI/SNW 2018, GTS takes part in a FFG research project to create a 3D TCAD model for ferroelectric materials.
Modeling and simulation of V-NAND poly-silicon channel trans-conductance, including variability
Presenting a Physical Modeling Study Based on 3D Phase-Space Subband Boltzmann Transport for Fully-Depleted SOI Technology
New applications: V-NAND transconductance variability, physical simulation of FD-SOI technology
Visit the GTS booth in the IEDM exhibits area to learn about our latest products and developments!
Introducing GTS local representative for East Asia
GTS was identified as one of the top 10 "Best Young SME" by the European Commission Innovation Radar 2017.
GTS workshops at two events in India, coordinated by our partner TNL.
TechNextLab becoming GTS partner for distribution and support in India.
Physical Modeling of Irradiation Effects in nano-scaled CMOS Logic and Memory Devices
Towards Physics-based DTCO for N7 and sub-N7 Technologies
TCAD-Based Characterization of Logic Cells: Power, Performance, Area, and Variability
GTS presenting TCAD modeling toolchain for irradition effects in nano-scale CMOS logic devices using layout-based design
GTS giving course at IMEC academy on march 29-30, 2017.Included is a hands-on session with multiple topics in the field of advanced CMOS simulation.