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GTS was identified as one of the top 10 "Best Young SME" by the European Commission Innovation Radar 2017.
GTS workshops at two events in India, coordinated by our partner TNL.
TechNextLab becoming GTS partner for distribution and support in India.
Physical Modeling of Irradiation Effects in nano-scaled CMOS Logic and Memory Devices
Towards Physics-based DTCO for N7 and sub-N7 Technologies
TCAD-Based Characterization of Logic Cells: Power, Performance, Area, and Variability
GTS presenting TCAD modeling toolchain for irradition effects in nano-scale CMOS logic devices using layout-based design
GTS giving course at IMEC academy on march 29-30, 2017.Included is a hands-on session with multiple topics in the field of advanced CMOS simulation.
GTS' paper 04.1 "Phase-Space Solution of the Subband Boltzmann Transport Equation for Nano-Scale TCAD" was ranked on third place.
In their 2016 IEDM paper, GTS scientists present latest results with direct implications on upcoming nanowire technologies.
CTO presenting GTS' unique and robust combination of SB-BTE, DD and Poisson approaches for reliable predictions of device performance
GTS scientists present a novel simulation approach for transport modeling in nano-scaled devices
GTS moves in to spacious office at central location in Vienna
GTS CTO to present simulation study on the feasibility of silicon as material for ultra-scaled nanowire field-effect transistors
Physical Modeling, Predictive Simulation of Future Devices – Path-Finding in the Final Stage of Device Scaling
Physics-based device simulation in practical use.
4 oral presentations – GTS scientists showing efficient solutions for layout-based device model generation, FinFET simulation, modeling of ultra-scaled transistors, and TCAD in the cloud
GTS Poster Session: New Computational Perspectives on Scattering and Transport in III/V Channel Materials
GTS to implement physics-based device simulation solution of 14nm fully-depleted SOI node and beyond
Complementing empirical models by physical ones is a breakthrough in nano-scaled device simulation. GTS researchers present their unique tools at the 2015 Silicon Nanoelectronics Workshop.