Global TCAD Solutions

Cutting-Edge TCAD

News

Events and Latest Developments at GTS

RSS Feed

We would love to inform you about relevant events and developments at GTS,
and welcome you to subscribe to our RSS newsfeed.
(We keep distortion to a minimum, not releasing more than ca. 12 items per year.)

13.07.2017

IEEE EDS Delhi Workshop, AICTE / IIT(BHU) Varanasi

GTS workshops at two events in India, coordinated by our partner TNL.

20.06.2017

New GTS Partner in India

TechNextLab becoming GTS partner for distribution and support in India.

31.05.2017

IWRMN-EDHE 2017 Invited Talk: From Impact to Upset

Physical Modeling of Irradiation Effects in nano-scaled CMOS Logic and Memory Devices

19.04.2017

Join our event at VLSI-TSA: DTCO for Advanced Nodes

Towards Physics-based DTCO for N7 and sub-N7 Technologies

12.04.2017

GTS @ VLSI-TSA Symposium Hsinchu, Taiwan

TCAD-Based Characterization of Logic Cells: Power, Performance, Area, and Variability

11.04.2017

GTS @ 12th ESA Geant4 Space Users Workshop

GTS presenting TCAD modeling toolchain for irradition effects in nano-scale CMOS logic devices using layout-based design

07.03.2017

IMEC Course: Advanced TCAD for sub-N7 FinFETs & Nanowires

GTS giving course at IMEC academy on march 29-30, 2017.Included is a hands-on session with multiple topics in the field of advanced CMOS simulation.

04.12.2016

SISPAD 2016 Best Paper Award: GTS among Top Three

GTS' paper 04.1 "Phase-Space Solution of the Subband Boltzmann Transport Equation for Nano-Scale TCAD" was ranked on third place.

21.11.2016

Identifying Crucial Aspects for Stacked NW FET - IEDM 2016

In their 2016 IEDM paper, GTS scientists present latest results with direct implications on upcoming nanowire technologies.

13.07.2016

GTS @ SISPAD 2016: SB-BTE for Nano-Scale CMOS

CTO presenting GTS' unique and robust combination of SB-BTE, DD and Poisson approaches for reliable predictions of device performance

13.06.2016

GTS @ VLSI / SNW 2016: Path-Finding, Dev. Optimization

GTS scientists present a novel simulation approach for transport modeling in nano-scaled devices

04.04.2016

New Headquarters in Vienna

GTS moves in to spacious office at central location in Vienna

20.01.2016

GTS Talk @ EUROSOI-ULIS: Feasibility of Silicon for Ultra-Scaled Nanowire FETs

GTS CTO to present simulation study on the feasibility of silicon as material for ultra-scaled nanowire field-effect transistors

12.11.2015

GTS @ IEDM 2015: Paper-Talk and Special Event

Physical Modeling, Predictive Simulation of Future Devices – Path-Finding in the Final Stage of Device Scaling

20.07.2015

From Atom To Transistor: Workshop+demo at ESSDERC 2015

Physics-based device simulation in practical use.

15.07.2015

4x GTS @ SISPAD 2015: Pushing the limits of TCAD

4 oral presentations – GTS scientists showing efficient solutions for layout-based device model generation, FinFET simulation, modeling of ultra-scaled transistors, and TCAD in the cloud

10.07.2015

IWCE 2015 (West Lafayette): Focus on III/V Materials

GTS Poster Session: New Computational Perspectives on Scattering and Transport in III/V Channel Materials

10.05.2015

WAYTOGO FAST: GTS providing TCAD solution for optimizing STMicroelectronics' 14nm SOI

GTS to implement physics-based device simulation solution of 14nm fully-depleted SOI node and beyond

06.05.2015

More Physics for Device Design – GTS @ SNW 2015

Complementing empirical models by physical ones is a breakthrough in nano-scaled device simulation. GTS researchers present their unique tools at the 2015 Silicon Nanoelectronics Workshop.

09.09.2014

SISPAD 2014: Accurate Modeling of Low-Field Mobilities

On the Validity of Momentum Relaxation Time in Low-Dimensional Carrier Gases