Global TCAD Solutions

Cutting-Edge TCAD


Events and Latest Developments at GTS

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We would love to inform you about relevant events and developments at GTS,
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(We keep distortion to a minimum, not releasing more than ca. 12 items per year.)


GTS @ IEDM 2017: Cell Simulation, DTCO

Visit the GTS booth in the IEDM exhibits area to learn about our latest products and developments!


Service Point in Taiwan R.O.C.

Introducing GTS local representative for East Asia


Listed by European Commission Innovation Radar 2017

GTS was identified as one of the top 10 "Best Young SME" by the European Commission Innovation Radar 2017.


IEEE EDS Delhi Workshop, AICTE / IIT(BHU) Varanasi

GTS workshops at two events in India, coordinated by our partner TNL.


New GTS Partner in India

TechNextLab becoming GTS partner for distribution and support in India.


IWRMN-EDHE 2017 Invited Talk: From Impact to Upset

Physical Modeling of Irradiation Effects in nano-scaled CMOS Logic and Memory Devices


Join our event at VLSI-TSA: DTCO for Advanced Nodes

Towards Physics-based DTCO for N7 and sub-N7 Technologies


GTS @ VLSI-TSA Symposium Hsinchu, Taiwan

TCAD-Based Characterization of Logic Cells: Power, Performance, Area, and Variability


GTS @ 12th ESA Geant4 Space Users Workshop

GTS presenting TCAD modeling toolchain for irradition effects in nano-scale CMOS logic devices using layout-based design


IMEC Course: Advanced TCAD for sub-N7 FinFETs & Nanowires

GTS giving course at IMEC academy on march 29-30, 2017.Included is a hands-on session with multiple topics in the field of advanced CMOS simulation.


SISPAD 2016 Best Paper Award: GTS among Top Three

GTS' paper 04.1 "Phase-Space Solution of the Subband Boltzmann Transport Equation for Nano-Scale TCAD" was ranked on third place.


Identifying Crucial Aspects for Stacked NW FET - IEDM 2016

In their 2016 IEDM paper, GTS scientists present latest results with direct implications on upcoming nanowire technologies.


GTS @ SISPAD 2016: SB-BTE for Nano-Scale CMOS

CTO presenting GTS' unique and robust combination of SB-BTE, DD and Poisson approaches for reliable predictions of device performance


GTS @ VLSI / SNW 2016: Path-Finding, Dev. Optimization

GTS scientists present a novel simulation approach for transport modeling in nano-scaled devices


New Headquarters in Vienna

GTS moves in to spacious office at central location in Vienna


GTS Talk @ EUROSOI-ULIS: Feasibility of Silicon for Ultra-Scaled Nanowire FETs

GTS CTO to present simulation study on the feasibility of silicon as material for ultra-scaled nanowire field-effect transistors


GTS @ IEDM 2015: Paper-Talk and Special Event

Physical Modeling, Predictive Simulation of Future Devices – Path-Finding in the Final Stage of Device Scaling


From Atom To Transistor: Workshop+demo at ESSDERC 2015

Physics-based device simulation in practical use.


4x GTS @ SISPAD 2015: Pushing the limits of TCAD

4 oral presentations – GTS scientists showing efficient solutions for layout-based device model generation, FinFET simulation, modeling of ultra-scaled transistors, and TCAD in the cloud


IWCE 2015 (West Lafayette): Focus on III/V Materials

GTS Poster Session: New Computational Perspectives on Scattering and Transport in III/V Channel Materials