Sub-threshold slope roll-off vs. gate length for Si and Ge-based PMOS NWFETs due to S/D-tunneling

Ubiquitous computing applications today are creating an ever increasing demand for custom Si chips in HPC, AI and telecommunications (5G). With the days of gate length scaling long gone, planar technologies (bulk, SOI) and non-planar technologies (FinFET) need to evolve constantly to keep up with requirements in terms of density, power, and performance, while navigating around the limitations imposed by device physics and fabrication processes.

Continuous advances in materials science, device technology and architectures are driving technology forward to satisfy these requirements by using new approaches that go beyond the state-of-the-art in Complementary Metal–Oxide–Semiconductor (CMOS) paradigm. Promising solutions include alternative device architectures, such as Nanowires (NW), Nanosheets (NS) or Gate all-around (GAA), and new materials for channel, insulators, and interconnects to better cope with fabrication issues and increase device performance and density.

With our suite of physical modeling tools for path-finding (including Minimos-NT, VSP, and NDS), you can easily, safely, and cost-effectively find your path to technological superiority.

Model Building

Universal mobility curve for a (100) silicon surface; lines: VSP simulation, symbols: measurements from Takagi et al., IEEE Trans. Electron. Dev. 41, 2357 (1994)

The attempt at detailed physical modeling of advanced MOSFET devices might be intimidating at first. Fortunately, GTS offers the right tools and proven procedures to successfully build your physical models. Leveraging the capabilities of our products VSP, Minimos-NT, and NDS, we employ a step-by-step guide that eliminates unknowns in a technology based on available characterization data.

Since VSP and NDS share the same band structure and scattering models, calibrated parameters can easily be transferred from one to the other, without a need to worry about consistency of the results.

 

 

Mobility curve for 14 nm FinFETs; green symbols: NMOS measurements, orange symbols: PMOS measurements, lines: VSP simulations; measurements from IMEC: Chiarella et al., 2016 ESSDERC, 131

Best Possible Performance

By default, VSP and NDS are calibrated to the “universal mobility” curves from Takagi et al., which provide a comprehensive set of data for planar silicon channels with different doping densities, orientation, and at different temperatures. The properties of the Si/SiO2 interface are representative of a mature technology. With a single set of parameters our simulators reproduce all of the universal mobility curves. This equips you with the capability to predict the best performance of your technology out of the box.

 

 

Transfer characteristic of 14 nm FinFET; lines: NDS simulation, dots: measurements from IMEC: Chiarella et al., 2016 ESSDERC, 131

Tailoring to Your Data

If data is available for specific technologies, doping profiles, Si/SiO2-interface non-idealities (surface-roughness, trap density), or contact resistivity can be extracted from characterization. Using the low-field transport models in VSP, interface properties such as roughness parameters or trap density can be adjusted to fit specific long-channel measurements. No long channel data available? NDS simulations of short channel devices can guide you to refined model parameters for your technology and can reveal difficult-to-determine parameters such as contact resistivity.

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GTS Nano Device Simulator – the first complete solution for effective physical simulation of nano-devices across technology nodes. Get profound predictive data for new materials and device architectures.

Path-Finding

Purely geometric scaling has stopped several nodes ago and the printed gate length are several times longer than their node name would indicate. Increasing device performance and density while maintaining power consumption and dissipation has become a difficult engineering challenge. Luckily, NDS is the right tool to support the development of current and future CMOS devices.

IMEC stacked NWFET technology – experiment vs. NDS simulations with different levels of scattering models included

The Bleeding Edge

As a well-calibrated tool, NDS can predict the electrical characteristics of novel device architectures. Want to introduce stacked nanowires while keeping most of the modules of your existing and mature FinFET process? NDS will reveal the best performance you can expect from the new architecture. Connecting NDS with your detailed process simulations is as simple as pushing a button. Looking for process options to fabricate your designs in two years from now? NDS lets you explore multiple emerging device architectures. Gate-all-around (GAA), nanosheets, SOI, or bulk FinFETs – with the flexibility and robustness of NDS, you’ll be certain to make the right decision.

 

 

NDS simulation of a planar FDSOI transistor using a non-parabolic 2-band k·p model; top left: electron concentration in FDSOI, bottom: distribution function in k-space at cuts indicated above, top right: 3D-phase-space plot of distribution function

Propelling Your Technology to New Heights

You are not working with the most recent technology nodes? What about planar and SOI technologies? NDS and VSP can help you grind away at the non-idealities of your technology. With the predictive power of NDS and VSP, you can assess what limits your device’s performance and where the fabrication process might need improvement: interface traps, contact resistance, interface roughness, doping profiles, etc. Even if your device is perfect for its application, it might not stay that way: NDS can help you investigate hot-carrier degradation and other processes detrimental to the reliability of your technology.

Get Accurate Results for Each Device Architecture

Being able to precisely predict and compare device performance significantly cuts the need for costly and time-consuming experiments. To get predictions that are valid on various nodes, device physics need to be considered – a big challenge in traditional TCAD.

GTS Nano Device Simulator (NDS) is the leading commercial TCAD tool fully leveraging predictive physical models to allow exploring and exploiting device physics at the nano scale, such as crystal orientation, strain, or material composition (e.g. Si-Ge). NDS opens up a new TCAD paradigm by capturing every important aspect of device operation at the nano scale and accurately reproducing measured device terminal characteristics.

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GTS Nano Device Simulator – the first complete solution for effective physical simulation of nano-devices across technology nodes. Get profound predictive data for new materials and device architectures.