Scientific Publications and White Papers by GTS Staff
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A multi-purpose Schrödinger-Poisson Solver for TCAD applications
We present the Vienna Schrödinger-Poisson Solver (VSP), a multi-purpose quantum mechanical solver for investigations on nano-scaled device structures. VSP includes a quantum mechanical solver for closed as well as open boundary problems on fairly arbitrary one-dimensional cross sections within the effective mass framework. For investigations on novel gate dielectrics VSP holds models for bulk and interface trap charges, and direct and trap assisted tunneling. Hetero-structured semiconductor devices, like resonant tunneling diodes (RTD), can be treated within the closed boundary model for quick estimation of resonant energy levels. The open boundary model allows evaluation of current voltage characteristics.
A Novel Approach to Modeling Insulator Wave-Function Penetration and Interface Roughness Scattering in MOSFETs
We present novel models for insulator wave-function penetration and for interface roughness scattering. We review the intricate relationship between modeling of these two effects, with respect to usability, computational effort, and numerical stability. We demonstrate that our novel approach is capable of remedying all of the common issues of previous approaches at no additional computational cost.
A TCAD Compatible SONOS Trapping Layer Model for Accurate Programming Dynamics
We present a TCAD model for the accurate de- scription of charging kinetics of trapping layers in 3D gate-all- around VNAND SONOS devices. We build on the established description of the trapping layer as trap-rich semiconductor and show that a strongly field-dependent carrier mobility greatly improves the reproduction of experimental incremental step pulse programming (ISPP) slopes. The resulting model was implemented in a commercial TCAD simulator and shown to accurately predict ISPP and retention loss measurement data with one consistent parameter set.
A Versatile Finite Volume Simulator for the Analysis of Electronic Properties of Nanostructures
We present a novel semantic approach to modeling and simulation of nanoelectronic devices. The approach is based on a finite volume spatial discretization scheme. The scheme was adapted to accurately treat material anisotropy. It is thus capable of capturing orientation and strain effects both of which are prominent in the nanoscale regime. We also demonstrate the method’s simplicity and power with a three-dimensional simulation study of a quantum dot using a six band k · p Hamiltonian for holes as model.
Adaptive Energy Integration of Non-Equilibrium Green’s Functions
To obtain the physical quantities of interest within the non-equilibrium Green’s function formalism, numerical integration over energy space is essential. Several adaptive methods have been implemented and tested for their applicability. The number of energy grid points needed and the convergence behaviour of the Schrödinger-Poisson iteration have been evaluated. An adaptive algorithm based on a global error criterion proved to be more efficient than a local adaptive algorithm.
Advanced Numerical Methods for Semi-classical Transport Simulation in Ultra-Narrow Channels
In this work we present a semi-classical modeling and simulation approach for ultra-narrow channels that has been implemented as part of the Vienna Schrödinger-Poisson (VSP) simulation framework (Baumgartner, J Comput Electron 12:701–721, 2013; http://www.globaltcad.com/en/products/vsp.html (2014)) over the past few years. Our research has been driven by two goals: maintaining high physical accuracy of the models while producing a computationally efficient and flexible simulation code.
Bringing Physics to Device Design – a Fast and Predictive Device Simulation Framework
We present a physically grounded modeling, simulation, and parameter-extraction framework that targets design and engineering of ultra-scaled devices and next-generation channel materials. The framework consists of a fast and accurate Schrödinger-Poisson solver/mobility extractor coupled to a device simulator. The framework brings physical modeling of semiconductor channels to device design and engineering which until now has been the domain of TCAD tools based on purely empirical models.
Cell Designer – a Comprehensive TCAD-Based Framework for DTCO of Standard Logic Cells
We present the first practical TCAD-based work flow for design-technology co-optimization (DTCO) of standard cells. The flow consists of parametric cell layout templates, layout-based structure generation, mixed-mode transient electri- cal device simulation, and data collection and analysis. Based on electrical and structural characterizations of the iN14, iN10, and iN7 nodes, the models presented in this work feature a projection for 5nm technology nodes based on FinFET, nanowire, and nanosheet. Transient five-stage ring-oscillator simulations show a clear advantage for the FinFET in terms of switching frequency and power consumption.
Comphy — A Compact-Physics Framework for Unified Modeling of BTI
Metal-oxide-semiconductor (MOS) devices are affected by generation, transformation, and charging of oxide and interface defects. Despite 50 years of research, the defect structures and the generation mechanisms are not fully understood. Most light has been shed onto the charging mechanisms of pre-existing oxide defects by using the non-radiative multi-phonon theory. In this work we present how the gist of physical models for pre-existing oxide defects can be efficiently abstracted at a minimal loss of physical foundation and accuracy. Together with a semi-empirical model for the generation and transformation of defects we establish a reaction-limited framework for unified simulation of bias temperature instabilities (BTI). The applications of the framework we present here cover simulation of BTI for negative (NBTI) and positive (PBTI) gate voltages, life time extrapolation, AC stress with arbitrary signals and duty cycles, and gate stack engineering.
Consistent Low-Field Mobility Modeling for Advanced MOS Devices
In this paper we develop several extensions to semi-classical modeling of low-field mobility, which are necessary to treat planar and non-planar channel geometries on equal footing. We advance the state-of-the-art by generalizing the Prange-Nee model for surface roughness scattering to non-planar geometries, providing a fully numerical treatment of Coulomb scattering, and formulating the Kubo-Greenwood mobility model in a consistent, dimension-independent manner. These extensions allow meaningful comparison of planar and non-planar structures alike, and open the door to evaluating emerging device concepts, such as the FinFET or the junction-less transistor, on physical grounds.
DTCO flow for air spacer generation and its impact on power and performance at N7
A novel DTCO flow is described with the principal aim to study the impact of air spacer fabrication on thernpower and performance of a 5-stage inverter ring oscillator at the 7 nm node. The flow incorporates physicalrnand analytical process models from the in-house ViennaPS simulation tool together with device and circuitrnsimulations from GTS Framework’s Cell Designer. The air spacer is usually filled by sequential conformal andrnnon-conformal deposition steps. The impact of the thickness of the conformal layer and the sticking probabilityrnduring non-conformal deposition on the ring oscillator performance is studied here. The air gap, which formsrnthe core of the air spacer, is generated during the non-conformal deposition step. We extract the relativerneffective permittivity of the air spacer as a function of these two fabrication parameters by solving the Poissonrnequation to obtain the spacer capacitance. Finally, SPICE model cards are extracted automatically from thernTCAD transistor characteristics and the parasitic network is calculated from the full 3D ring oscillator logicrncell using a field solver. We apply our framework on two fabrication flows, when the air gap is created beforernand after the deposition of the first metal contacts layer. We observe that introducing the air gap inside thernspacer results in an at-least 15% improvement in the ring oscillator’s performance, when the power is keptrnconstant. Further improvements can be achieved by reducing the conformal layer thickness and increasing thernsticking probability by increasing the chamber partial pressure or increasing the process temperature.
Efficient Modeling of Source/Drain Tunneling in Ultra-Scaled Transistors
In this work, a comprehensive investigation of the effect of source/drain tunneling in ultra-scaled transistors is presented. A novel approach to efficiently and accurately incorporate the quantum-mechanical effects of source/drain (S/D) tunneling in semi-classical device simulators has been developed. The ballistic quantum transport model has been implemented as part of the Vienna-Schrödinger-Poisson simulation and modeling framework. The transport formalism is based on the quantum transmitting boundary method and has been extended to provide recombination and generation rates of carriers due to the direct tunneling current across the source/drain barrier. The model has been used to investigate the effect of direct S/D tunneling on device performance in ultra-scaled double-gate and nanowire transistors. The variations in transfer and output characteristics due to the tunneling effect have been calculated for different gate lengths and channel widths. The influence on the drain induced barrier lowering is shown.
Expanding TCAD Simulations from Grid to Cloud
In this work, the distribution, execution and performance of TCAD simulations on grid and cloud systems are investigated. A module for distributed computing which can uniformly interface both grid and cloud computing systems has been implemented within GTS Framework. Automated allocation of resources for user jobs on a combined platform has been achieved. Traditional grid-computing systems are compared with cloud-based systems. Strategies for cost-effective allocation of cloud-resources are presented. The performance of a typical TCAD application run on a grid, in the cloud, and a hybrid system combining both are assessed.
Exploring the Design Space of Non-Planar Channels: Shape, Orientation, and Strain
We conduct a comprehensive simulation study of non-planar n-type channels based on consistent, physical models containing measurable quantities rather than fit-parameters. This contrasts empirical thin-body models used in classical/quantum-corrected TCAD. The method involves the self-consistent solution of the two-dimensional Schrödinger-Poisson system,rncombined with linearized Boltzmann transport in the third dimension. We advance the art of simulation by (i) introducing quantum simulation on unstructured meshes for arbitraryrngeometries, (ii) providing an efficient framework for rapid evaluation of device designs, and (iii) contributing a surface roughness scattering model for arbitrarily shaped surfaces.rnConsistent modeling allows us to make reliable assertions with respect to device performance.
Fast Methods for Full-Band Mobility Calculation
We developed a number of methods targeted at fast full-band mobility calculation of device channels, including: subband structure calculation, determination of couplings in k-space, and evaluation of the transition rates based on our recent modeling efforts of SRS. The entire workflow is implemented within the Vienna Schrödinger-Poisson (VSP) simulation framework. Every step in the process is parallelized with close-to-linear scalability. The resulting performance boost brings full-band mobility modeling one significant step closer tornmainstream TCAD device simulation.
From Gate Oxide Characterization to TCAD Predictions: Exploring Impact of Defects Across Technologies
Despite extensive modeling efforts, not all semiconductor fabrication processes are fully understood on a physical level and phenomenological tools are used to analyze process splits. This works well for incremental improvements but has limitations when it comes to more fundamental developments. TCAD simulators, on the other hand, offer physical models and consider non-homogeneous field distributions and the effect of discrete charges. However, they are considerably more complex to use and to parametrize which can make them impractical. Therefore, the efficient gate stack simulator Comphy was presented recently which is used to extract physical defect properties. In this work, a development strategy is presented which employs this extraction methodology followed by an import of the defect parameters in a TCAD simulator. Using the same gate stack on different geometries we study the degradation and time dependent variability which increases from planar MOSFETs to FinFETs and is even worse for nanowires.
Full (Vg, Vd) Bias Space Modeling of Hot-Carrier Degradation in Nanowire FETs
Simulations of hot-carrier degradation of nanowire field-effect transistors are reported. The simulations rely on the carrier energy distribution function, obtained by solving the Boltzmann transport equation. To model the contribution of impact ionization, the hydrodynamic scheme is employed. A range of pertinent physical mechanisms is invoked and discussed to adequately reproduce HCD measurements in the full (Vg, Vd) bias space. Impact ionization is discussed as an important ingredient of HCD at low gate, high drain voltages.
Full-Band Modeling of Mobility in p-type FinFETs
We present a framework for modeling the low-field mobility of ultra-narrow Si channels such as FinFETs based on a full-band description of the electronic structure. Hole mobility is of particular interest since its calculation necessitates a full-band approach. Our approach is entirely based on physical modeling and thus naturally includes effects of gate field, crystal orientation, or strain.
Hierarchical TCAD Device Simulation of FinFETs
A framework for FinFET design studies is presented. Our physics-based modeling approach allows to accurately capture the effects of channel cross-section, orientation and strain as well as contact resistance - for the first time all in one tool. Using this approach as a reference, the predictiveness of empirical TCAD models is extended by re-calibration. Our hierarchical tool chain is embedded in an industry-proven framework equipped with DOE and optimization modules. The capabilities are demonstrated in a simulation study on a recent FinFET technology node.
Investigation of Quantum Transport in Nanoscaled GaN High Electron Mobility Transistors
In this paper, a comprehensive investigation of quantum transport in nanoscaled gallium nitride (GaN) high electron mobility transistors (HEMTs) is presented. A simulation model for quantum transport in nanodevices on unstructured grids in arbitrary dimension and for arbitrary crystal directions has been developed. The model has been implemented as part of the Vienna-Schrödinger-Poisson simulation and modeling framework. The transport formalism is based on the quantum transmitting boundary method. A new approach to reduce its computational effort has been realized. The model has been used to achieve a consistent treatment of quantization and transport effects in deeply scaled asymmetric GaN HEMTs. The self-consistent electron concentration, conduction band edges and ballistic current have been calculated. The effects of strain relaxation at the heterostructure interfaces on the potential andrncarrier concentration have been shown.
Layout-Based TCAD Device Model Generation
In this work, a fully automated process emulation is presented. Starting from industrial standard gdsII mask files a user friendly and fast way to create TCAD ready models has been realized. A three step approach is used. The creation of virtual layers to allow for logical operation based on masks is shown. Then the geometrical and dopant profile instantiation is carried out. Third the mesh generation based on and optimized on the information of the first two steps is shown. Industry-relevant sample applications for the implemented work-flow ranging from a radiation hardened latch to a state of the art FinFET SRAM cell are demonstrated.
Modeling Direct Band-to-Band Tunneling using QTBM
This work focuses on modeling the tunneling mechanism in direct semiconductors. An effective barrier is extracted between the valence and conduction band, by defining the barrier as valence-like near the valence band and conduction band-like near the conduction band. The transition occurs at a point obtained by momentum matching. Computation of transition coefficient is performed using the quantum transmitting boundary method.
Modeling Surface-Roughness-Induced Scattering in Non-Planar Silicon Nanostructures
We extend the surface roughness scattering formalism for planar structures to non-planar ones. The planar-structure formalism based on theory by Prange and Nee [1] has been widely used for calculating the conductivity of inversion layers and thin films [2]. An extension to cylindrical nanowires has been developed by Jin et al. [3]; their model assumes isotropic band structure in the channel matrial and assigns radial and angular quantum numbers to each state thus facilitating the evaluation of the surface roughness matrix elements. We derive matrix elements for open and closed surfaces of arbitrary shape taking anisotropy of the band structure fullyrninto account. This model is applied to different device cross-sections such as a FinFET or a nanowire.
Monolithic TCAD Simulation of Phase-Change Memory (PCM/PRAM) + Ovonic Threshold Switch (OTS) Selector Device
Owing to the increasing interest in the commercialization of phase-change memory (PCM) devices, a number of TCAD models have been developed for their simulation. These models formulate the melting, amorphization and crystallization of phase-change materials as well as their extreme conductivity dependence on both electric field and temperature into a set of self-consistently-solved thermoelectric and phase-field partial-differential equations. However, demonstrations of the ability of such models to match actual experimental results are rare. In addition, such PCM devices also require a so-called selector device - such as an Ovonic Threshold Switching (OTS) device - in series for proper memory operation. However, monolithic simulation of both the PCM and OTS selector device in a single simulation is largely absent from the literature, despite its potential value for material- and design-space explorations. It is the goal of this work to first characterize a PCM device in isolation against experimental data, then to demonstrate the qualitative behavior of a simulated OTS device in isolation and finally to perform a single monolithic simulation of the PCM + OTS device within the confines of a commercially available TCAD solver: GTS Framework.
Nano Device Simulator—A Practical Subband-BTE Solver for Path-Finding and DTCO
We present an in-depth discussion on the subband Boltzmann transport (SBTE) methodology, its evolution, and its application to the simulation of nanoscale MOSFETs. The evolution of the method is presented from the point of view of developing a commercial general-purpose SBTE solver, the GTS nano device simulator (NDS). We show a wide range of applications SBTE is suited for, including state-of-the-art nonplanar and well-established planar technologies. It is demonstrated how SBTE can be employed both as a path-finding tool and a fundamental component in a DTCO-flow.
New Computational Perspectives on Scattering and Transport in III/V Channel Materials
A physically-grounded modeling, simulation, and parameter-extraction framework that targets design and engineering of ultra-scaled devices and next-generation channel materials. The framework consists of a fast and accurate Schrdinger-Poisson solver/mobility extractor coupled to a device simulator. It brings physical modeling of semiconductor channels to device design and engineering which until now has been the domain of TCAD tools based on purely empirical models. In this work, we specifically explore the framework components required to model devices based on III/V compound semiconductors.
On the feasibility of DoS-engineering for achieving sub-60 mV subthreshold slope in MOSFETs
We present the operating principle of an ideal Cold Source Field Effect Transistor and check the DoS source engineering impact on its subthreshold slope. The Subband Boltzmann Transport Equation is solved and the resulting transfer curves in the ballistic regime are presented, as well as those including the effects of scattering. The inclusion of scattering reveals its importance in the rethermalization of the cold carriers at the source extension and the degradation in the static leakage of the device. Finally, we show the impact in the SS when substituting the semiconducting source extension by the cold metal.
On the Modeling of Polycrystalline Ferroelectric Thin Films: Landau-Based Models Versus Monte Carlo-Based Models Versus Experiment
Due to the potential for technological application, there has been an explosion of interest in heavily polycrystalline ferroelectric nanofilms, such as those of doped hafnium oxide. However, the heavily polycrystalline nature of these materials invalidates conventional model- ing approaches as the dynamics have been found to be: 1) nucleation-limited; 2) involve grains of ferroelectric material interspersed among grains of alternative, nonferroelectric material; and 3) the direct interaction between these grains is observed to be minimal. In this article, we con- sider seven separate compact or "0-D" models of such polycrystalline films. Four of these models are based on a Landau paradigm and two are based on a Monte Carlo (MC) paradigm. The seventh is the traditional Preisach model. Although all of these models have been used in the literature to model novel polycrystalline ferroelectric nanofilms, here we compare and contrast the accuracy and physical appro- priateness of each model by comparing both their static and dynamic properties against experimental data. We then find that although all models except single-grain models are capable of reproducing the static properties, only the MC models replicate the long-time dynamical properties. Thus, it is demonstrated that not all models are equally valid for the accurate modeling of such films.
On the Validity of Momentum Relaxation Time in Low-Dimensional Carrier Gases
The momentum relaxation time (MRT) is widely used to simplify low-field mobility calculations including anisotropic scattering processes. Although not always fully justified, it has been very practical in simulating transport in bulk and in direction quantity low-dimensional carrier gases alike. We review the assumptions behind the MRT, quantify the error introduced by its usage forrnlow-dimensional carrier gases, and point out its weakness in accounting for inter-subband interaction, occurring specifically at low inversion densities.
Performance and Leakage Analysis of Si and Ge NWFETs Using a Combined Subband BTE and WKB Approach
We are the first to present a subband-BTE solver with a fully integrated source/drain-tunneling current calculation based on the WKB-approximation. The method is validated against ballistic NEGF calculations showing good agreement. An investigation of Si and Ge-based NWFETs is performed showing that intra-band source/drain-tunneling is not a concern for Si devices. For Ge-based PMOS devices however, tunneling leakage limits sensible LG -scaling to around 20 nm.
Performance and Variability-Aware SRAM Design for Gate-All-Around Nanosheets and Benchmark with FinFETs at 3nm Technology Node
For the 3nm technology node, horizontal gate-all- around nanosheet devices offer a non-disruptive process tran- sition from fin technologies with the advantage of full 3D design flexibility and better short-channel control. For SRAM cell design, this enables non-digital n/pFET balancing. In this paper, a performance and variability-aware DTCO flow is used to benchmark nanosheet SRAM cells against fin technologies at 3nm node, targeted at 45 nm CPP and 21 nm MP. The impact of gate length, fin height, number of nanosheets, effective n/pFET widths, channel doping, and vertical nanosheet pitch is studied. Despite the lower parasitic capacitances of fins, the design freedoms of nanosheets enable superior SRAM operation in terms of both Vmin and read delay even at smaller cell areas.
Phase-Space Solution of the Subband Boltzmann Transport Equation for Nano-Scale TCAD
We present a comprehensive simulation framework for transport modeling in nano-scaled devices based on the solution of the subband Boltzmann transport equation (BTE). The BTE is solved in phase space using a k·p-based electronic structure model and includes all relevant scattering processes. The BTE solver is combined with a conventional drift-diffusion- based simulator using a novel iteration approach. The pairing between BTE, DD, and Poisson results in a flexible toolkit which converges quickly in any mode of operation, allows large- scale parallelization, and to include near-equilibrium transport outside the BTE region, i.e. the contacting regions. The toolkit is commercially available as part of the GTS Nano Device Simulator (NDS). We examine realistic NMOS and PMOS devices, includ- ing transport at the microscopic scale and possible numerical approximations.
Physical Modeling – a New Paradigm in Device Simulation
We go far beyond classical TCAD in and create a simulation framework that is ready for devices based on contemporary and future technology nodes. We do so by extending the common drift-diffusion-type device simulation framework with additional tools: (i) a k p-based subband structure tool, (ii) a deterministic subband Boltzmann transport solver, and (iii) a TCAD-compatible quantum transport solver, to capture every important aspect of device operation at the nano-scale. An atomistic ab-initio tool suite complements the framework providing material properties that would be hard to obtain otherwise. The capabilities of the approach are demonstrated on two different devices featuring non-planar geometry and alternative channel materials.
Physical Transport Simulation for Path-Finding and Device Optimization
We present a novel simulation approach for transport modeling in nano-scaled devices. It is based on the solution of the Boltzmann transport equation (BTE) in phase space using a k·p-based electronic structure model and includes all relevant scattering processes. The modeling framework is suitable low and high VDD regime and consistently covers all the necessary physics like confinement, velocity overshoot, and quantum resistance to give meaningful predictions using only few material parameters. With a highly efficient numerical implementation, the approach is suitable for both path-finding and device optimization.
Predictive Physical Simulation of III/V Quantum-Well MISFETs for Logic Applications
We present a simulation modeling chain for nano-scaled III/V quantum-well MISFETs. Our methods are based on physical rather than empirical modeling, which allows to obtain predictive simulation results with very few fitting parameters. We use a recent InGaAs-based technology from Intel [1] to validate our simulation results which show excellent agreement with measured capacitance and conductance curves. We further evaluate the properties of a 60 nm long InGaAs quantum-well transistor, finding a sub-threshold slope of 73.5 mV/dec and a DIBL of 103.8 mV/V. A fast numerical computational framework ensures high modeling flexibility; at the same time execution times are kept short making our approach an ideal replacement for empirical device modeling which is still pervasive in TCAD.
Quasi-Fermi-Based Charge Transport Scheme for Device Simulation in Cryogenic, Wide Bandgap, and High-Voltage Applications
We present a novel approach to solving the transport problem in semiconductors. We reformulate the drift-diffusion (DD) equations in terms of the quasi- Fermi-energies as solution variables; a drastic increase in numerical stability is achieved, which permits the simulation of devices at cryogenic temperatures as well as wide bandgap devices using double precision arithmetic, instead of extended precision arithmetic which would otherwise be required to solve these applications using regular DD.
Reliability and Variability-Aware DTCO Flow: Demonstration of Projections to N3 FinFET and Nanosheet Technologies
Reliability and variability-aware simulations of logic cells are essential to correctly analyze and predict the performance of upcoming technologies. A simulation flow for DTCO is presented here, which combines the accuracy of TCAD with the performance of SPICE - utilizing parasitic extractions, the impedance field method for variations, and the compact-physics simulator comphy for reliability. Good agreement with experimental RO performance of N14 is demonstrated and projections to N3 FinFET and nanosheet technologies are made.
Scaling FDSOI Technology down to 7 nm – a Physical Modeling Study Based on 3D Phase-Space Subband Boltzmann Transport
We present the first truly full-band approach to solving the subband Boltzmann transport (SBTE) equation in three-dimensional phase space. The solution is applied to investigate the evolution of the FDSOI MOSFET towards the 7nm node. Our findings show that single-gate FDSOI technology can be effectively scaled down to the 14 nm node, because the on-current gains are large enough to offset the SS-degradation. Beyond 14 nm a double-gate thin-body geometry is required to maintain electrostatic control.
Simulation Study on the Feasibility of Si as Material for Ultra-Scaled Nanowire Field-Effect Transistors
We present a simulation framework which allows thorough performance evaluation of ultra-scaled devices. Our simulation approach is based on the full solution of the Boltzmann transport equation (BTE) on subbands as calculated from a k·p-Hamiltonian and including all relevant scattering mechanisms which occur in semiconductors at room temperature. We employ the simulation framework to investigate the performance limits of silicon-based technology for ultra-scaled field-effect transistors in logic applications.
Surface-Roughness-Scattering in Non-Planar Channels – the Role of Band Anisotropy
We developed a new generic method for evaluating the surface-roughness-induced scattering rate in non-planar semiconductor structures. The method accurately captures band anisotropy and the roughness-induced momentum transfer between the confined states. Strong dependence of SRS-limited electron mobility on crystal orientation was observed with and [110]/(11̄0) being the optimal orientations.
TCAD-Based Characterization of Logic Cells: Power, Performance, Area, and Variability
We present a novel approach for extracting the power-performance-area PPA parameter and their variability directly from a TCAD model of a logic cell. The process involves layout-based structure generation based on technology description files, transient device simulation, and parameter extraction of timing delays and power consumption. Different sources of global and local variability can be added to investigate the sensitivity of timing and power parameters. The entire process is quick and fully automated from GDSII file to PPA characteristics, and is thus suitable for use by cell and circuit designers. The extracted parameters and statistics can be directly used in high-level descriptions of digital circuits and systems.
The Impact of Parasitic Capacitances on NCFET Performance – a TCAD Study
We investigate the effectiveness of the performance boost provided through ferro-electric materials in negative-capacitance FETs (NCFETs) using a hybrid TCAD/compact modeling approach. We show that, in a practical device, the performance boost is dominated by parasitic capacitances. The impact of the doping profile on NCFET performance is studied showing that tight control of the doping is required to maintain the boost in highly scaled devices.
Towards Physics-Based DTCO for Performance of Advanced Technology Nodes
We present a case study which shows the path towards design-technology co-optimization (DTCO) based on physical device modeling as opposed to simulation based on empirical mobility models. This allows for more accurate and robust predictions of device performance, and allows to assess novel process options found in 7 nm and 5 nm technology nodes. A more than ten-fold increase in computational efficiency brings turn-around times down sufficiently to make physical models suitable for the DTCO process.
Understanding the ISPP Slope in Charge Trap Flash Memory and its Impact on 3-D NAND Scaling
We present a physical modeling approach that explains the non-ideal ISPP slope in charge trap layer (CTL) flash memory and its impact on 3-D NAND vertical pitch scaling. First, we derive an expression for the VT change rate and use its field dependence to reproduce experimental vertical NAND ISPP slopes. Next, we implement a 2.5-D TCAD model based on these insights and show significant program voltage increase (>5V) in realistic 3-D NAND flash devices with scaling vertical pitch (down to 10nm). Finally, we evaluate high-k CTL and airgaps as mitigation measures at scaled pitch.
Variability-Aware DTCO Flow: Projections to N3 FinFET and Nanosheet 6T SRAM
Variability increases with downscaling, making it a vital component in the assessment of upcoming technologies. We use a variability-aware DTCO flow, which seamlessly integrates accurate TCAD simulations with industry-proven SPICE solutions. The impact of local variability sources on SRAM KPIs is analyzed for N3 FinFET and nanosheet technologies. Assuming typical process parameters, the geometrical variations due to LWR, STI recess, and epitaxial growth significantly affect the SRAM variability. However, the main contributor to variability for N3 technologies is MGG, highlighting the crucial role of metal grains size reduction for technology optimization.
Vertically Stacked Nanowire MOSFETS for Sub-10 nm Nodes: Advanced Topography, Device, Variability, and Reliability Simulations
Using an advanced simulation framework we analyze a recent sub-10 nm technology demonstration based on stacked nanowire transistors (NW-FETs). The study encompasses (i) topography simulation which realistically reproduces the fabricated device, (ii) device simulation based on the subband Boltzmann transport equation (iii) a comprehensive set of scattering models for the gate stack, (iv) physical models for time-zero variability and BTI device degradation. We find that (i) the fabrication process introduces parasitic capacitances not present in a comparable FinFET, (ii) the device performance is significantly affected by interface-charge-induced Coulomb scattering resulting in up to 50% reduction in drain current compared to an ideal device, (iii) device time-zero variability is increased due to a lower amount of dopant atoms per device, (iv) the device is more affected by BTI than a comparable FinFET. Using physics-based TCAD for technology path-finding and device optimization, we are able to point out critical improvements required for the stacked NW-FET to surpass current FinFET technology.
VSP – A Quantum-Electronic Simulation Framework
The Vienna Schrödinger-Poisson (VSP) simulation framework for quantum-electronic engineering applications is presented. It is an extensive software tool that includes models for band structure calculation, self-consistent carrier concentrations including strain, mobility, and transport in transistors and heterostructure devices. The basic physical models are described. Through flexible combination of basic models sophisticated simulation setups for particular problems are feasible. The numerical tools, methods and libraries are presented. A layered software design allows VSP’s existing components such as models and solvers to be combined in a multitude of ways, and new components to be added easily. The design principles of the software are explained. Software abstraction is divided into the data, modeling and algebraic level resulting in a flexible physical modeling tool. The simulator’s capabilities are demonstrated with real-world simulation examples of tri-gate and nanoscale planar transistors, quantum dots, resonant tunneling diodes, and quantum cascade detectors.